IS42S16100E, IC42S16100E
Read Cycle, Write Cycle / Burst Read, Single Write
T11
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
tCHI
tCKS
tCL
tCK
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
t
AS
AS
t
AH
(1)
(1)
COLUMN m
COLUMN n
AUTO PRE
ROW
ROW
A0-A9
A10
BANK 0 AND 1
BANK 0 OR 1
t
AH
AH
NO PRE
BANK 1
NO PRE
t
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
A11
BANK 0
t
CS
t
CH
t
QMD
DQM
DQ
tAC
t
AC
t
DS
t
OH
t
OH
t
DH
D
OUT
m
D
OUT m+1
DIN
n
t
LZ
t
HZ
tRC
tCAC
t
DPL
t
RAS
RC
t
RP
t
<
WRIT
>
<
PRE
>
<
ACT>
<
READ>
Undefined
Don't Care
CAS latency = 3, burst length = 2
Note 1: A8,A9 = Don’t Care.
78
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08