IS42S16100E, IC42S16100E
Write Cycle / Page Mode; Data Masking
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CLK
tCHI
tCKS
tCK
t
CL
CKE
CS
t
t
CKA
tCS
CH
t
CS
tCH
tCH
tCH
RAS
t
CS
CS
CAS
WE
t
t
AS
AS
t
AH
(1)
(1)
(1)
COLUMN m
ROW
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
A10
BANK 0 AND 1
BANK 1OR 0
t
t
t
AH
AH
NO PRE
NO PRE
NO PRE
BANK 1
BANK 0
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
A11
tCS
tCH
DQM
DQ
t
DH
t
DH
t
DH
tDS
tDS
t
DH
t
DS
t
DH
tDS
t
DS
D
IN n
D
IN
o
D
IN
m
D
IN o+1
D
IN m+1
t
RCD
t
DPL
tRAS
t
RP
tRC
<
ACT>
<WRIT
>
<
WRIT>
<
MASK>
<
WRIT
>
<
PRE
>
Undefined
Don't Care
CAS latency = 3, burst length = 2
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com
71
Rev. C
01/22/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
