IS42S16100E, IC42S16100E
Read Cycle / Full Page
T0
T1
T2
T3
T4
T5
T6
T7
T8
T262
T263
T264
T265
CLK
t
CHI
tCKS
tCL
tCK
CKE
CS
t
t
CKA
t
CS
CH
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
COLUMN
ROW
ROW
A0-A9
t
AH
AH
NO PRE
BANK 0
A10
A11
BANK 0 OR 1
BANK 0
t
t
AS
BANK 0
t
CH
t
CS
DQM
DQ
t
AC
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
t
OH
t
OH
D
OUT 0m
D
OUT 0m+1
D
OUT 0m-1
D
OUT 0m
D
OUT 0m+1
t
LZ
t
HZ
t
RCD
(BANK 0)
RAS
(BANK 0)
t
CAC
tRBD
(BANK 0)
t
RP
t
(BANK 0)
t
RC
(BANK 0)
ACT 0
Undefined
Don't Care
CAS latency = 3, burst length = full page
Note 1: A8,A9 = Don’t Care.
62
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08