IS42S16100E, IC42S16100E
PIN CONFIGURATION
PACKAGE CODE: B 60 BALL FBGA (Top View) (10.1 mm x 6.4 mm Body, 0.65 mm Ball Pitch)
1 2 3 4 5 6 7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
PIN DESCRIPTIONS
A0-A10
A0-A7
A11
DQ0 to DQ15
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
LDQM, UDQM
V
dd
Vss
V
ddq
Vss
q
NC
Write Enable
x16 Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
VSS DQ15
DQ14 VSSQ
DQ13 VDDQ
DQ12 DQ11
DQ10 VSSQ
DQ9 VDDQ
DQ8
NC
NC
NC
DQ0
VDD
VDDQ DQ1
VSSQ DQ2
DQ4
DQ3
VDDQ DQ5
VSSQ DQ6
NC
VDD
LDQM
RAS
NC
NC
A0
A2
A3
DQ7
NC
WE
CAS
CS
NC
A10
A1
VDD
NC UDQM
NC
CKE
A11
A8
A6
VSS
CLK
NC
A9
A7
A5
A4
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
