IS42S16100E, IC42S16100E
Mode Register Set Command
(CS, RAS, CAS, WE = LOW)
When the A10 pin is HIGH, this command functions as a
read with auto-precharge command. After the burst read
completes, the bank selected by pin A11 is precharged.
When the A10 pin is LOW, the bank selected by the A11
pin remains in the activated state after the burst read
completes.
The IS42S16100E/IC42S16100E product incorporates
a register that defines the device operating mode. This
command functions as a data input pin that loads this
register from the pins A0 to A11. When power is first
applied, the stipulated power-on sequence should be
executed and then the IS42S16100E/IC42S16100E
should be initialized by executing a mode register set
command.
Write Command
(CS, CAS, WE = LOW, RAS = HIGH)
Note that the mode register set command can be
executed only when both banks are in the idle state (i.e.
deactivated).
When burst write mode has been selected with the mode
register set command, this command selects the bank
specified by the A11 pin and starts a burst write operation
at the start address specified by pins A0 to A9. This first
data must be input to the DQ pins in the cycle in which
this command.
Another command cannot be executed after a mode
registersetcommanduntilafterthepassageoftheperiod
tm c d , which is the period required for mode register set
command execution.
The selected bank must be activated before executing
this command.
Active Command
(CS, RAS = LOW, CAS, WE= HIGH)
When A10 pin is HIGH, this command functions as a
write with auto-precharge command. After the burst write
completes, the bank selected by pin A11 is precharged.
When the A10 pin is low, the bank selected by the A11
pin remains in the activated state after the burst write
completes.
The IS42S16100E/IC42S16100E includes two banks of
2048 rows each. This command selects one of the two
banks according to the A11 pin and activates the row
selected by the pins A0 to A10.
After the input of the last burst write data, the application
must wait for the write recovery period (td p l , td a l ) to elapse
according to CAS latency.
This command corresponds to the fall of the RAS signal
from HIGH to LOW in conventional DRAMs.
Precharge Command
(CS, RAS, WE = LOW, CAS = HIGH)
Auto-Refresh Command
(CS, RAS, CAS = LOW, WE, CKE = HIGH)
This command starts precharging the bank selected by
pins A10 and A11. When A10 is HIGH, both banks are
precharged at the same time. When A10 is LOW, the
bank selected by A11 is precharged. After executing this
command, the next command for the selected bank(s)
is executed after passage of the period tr p , which is the
period required for bank precharging.
This command executes the auto-refresh operation. The
row address and bank to be refreshed are automatically
generated during this operation.
Bothbanksmustbeplacedintheidlestatebeforeexecuting
this command.
The stipulated period (tr c ) is required for a single refresh
operation, and no other commands can be executed
during this period.
This command corresponds to the RAS signal from LOW
to HIGH in conventional DRAMs
The device goes to the idle state after the internal refresh
operation completes.
Read Command
(CS, CAS = LOW, RAS, WE = HIGH)
This command must be executed at least 4096 times
every 64 ms.
This command selects the bank specified by the A11 pin
and starts a burst read operation at the start address
specified by pins A0 to A9. Data is output following CAS
latency.
This command corresponds to CBR auto-refresh in
conventional DRAMs.
The selected bank must be activated before executing
this command.
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
