IC41C82052
IC41LV82052
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min. Max.
Unit
IIL
Input Leakage Current
Any input 0V < VIN < Vcc
Other inputs not under test = 0V
5
5
2.4
5
µA
IIO
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Standby Current: TTL
Output is disabled (Hi-Z)
0V < VOUT < Vcc
5
µA
V
VOH
VOL
ICC1
ICC2
ICC3
IOH = 5.0 mA with VCC=5V
IOH = 2.0 mA with VCC=3.3V
0.4
IOL = 4.2 mA with VCC=5V
IOL = 2 mA with VCC=3.3V
V
RAS, CAS > VIH
5V
3.3V
2
0.5
mA
mA
mA
Standby Current: CMOS
RAS, CAS > VCC 0.2V
5V
3.3V
1
0.5
Operating Current:
Random Read/Write(2,3,4)
Average Power Supply Current
RAS, CAS,
Address Cycling, tRC = tRC (min.)
-50
-60
120
110
ICC4
ICC5
ICC6
Operating Current:
&ast Page Mode(2,3,4)
Average Power Supply Current
RAS = VIL, CAS,
tRC = tRC (min.)
-50
-60
90
80
mA
mA
mA
Refresh Current:
RAS-Only(2,3)
Average Power Supply Current
RAS Cycling, CAS > VIH
tRC = tRC (min.)
-50
-60
120
110
Refresh Current:
CBR(2,3,5)
Average Power Supply Current
RAS, CAS Cycling
tRC = tRC (min.)
-50
-60
120
110
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREꢀ refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
Integrated Circuit Solution Inc.
DR015-0A 06/12/2001
5
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
