IC41C82052
IC41LV82052
ꢀUNCTIONAL BLOCK DIAGRAM
OE
WE
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
CAS
CONTROL
LOGIC
CAS
CAS
WE
DATA I/O BUS
RAS
CLOCK
RAS
GENERATOR
COLUMN DECODERS
SENSE AMPLIFIERS
REFRESH
COUNTER
I/O0-I/O7
MEMORY ARRAY
2,097,152 x 8
ADDRESS
BUFFERS
A0-A10
TRUTH TABLE
ꢀunction
Standby
Read
RAS
CAS
WE
X
OE
X
Address tR/tC I/O
H
L
L
L
H
L
L
L
X
High-Z
H
L
ROW/COL
ROW/COL
ROW/COL
DOUT
Write: Word (Early Write)
Read-Write
L
X
DIN
H→L
L→H
DOUT, DIN
Hidden Refresh
Read
Write(1)
L
→
H
H
→
→
L
L
L
L
H
L
L
ROW/COL
ROW/COL
DOUT
DOUT
L→
X
RAS-Only Refresh
L
H
L
X
X
X
X
ROW/NA
X
High-Z
High-Z
CBR Refresh
H→L
Note:
1. EARLY WRITE only.
2
Integrated Circuit Solution Inc.
DR015-0A 06/12/2001
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
