AS7C33512NTF18A
®
Synchronous truth table
[5,6,7,8,9
]
CE0
CE1 CE2 ADV/LD R/W
BWn
OE
CEN
Address
source
CLK
Operation
DQ
Notes
H
X
X
X
L
X
L
X
L
X
L
X
X
X
X
L
X
H
X
H
X
H
X
H
X
X
X
H
X
X
L
X
L
X
L
X
L
X
X
L
L
L
H
L
H
L
H
L
H
L
H
X
X
X
X
X
H
X
H
X
L
X
L
X
X
X
X
X
X
X
X
X
X
L
L
H
H
X
X
X
X
X
L
L
H
H
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
H
NA
NA
NA
NA
Next
Next
Next
L to H
L to H
L to H
L to H
L to H
L to H
L to H
DESELECT Cycle
DESELECT Cycle
DESELECT Cycle
CONTINUE DESELECT Cycle
READ Cycle (Begin Burst)
READ Cycle (Continue Burst)
DUMMY READ (Continue Burst)
WRITE CYCLE (Begin Burst)
WRITE CYCLE (Continue Burst)
High-Z
High-Z
High-Z
High-Z
Q
Q
1,10
2
3
1,3,10
2,3
1,2,3,
10
4
1
External L to H
External L to H NOP/DUMMY READ (Begin Burst) High-Z
External L to H
D
D
High-Z
High-Z
-
High-Z 1,2,10
External L to H NOP/WRITE ABORT (Begin Burst)
Next
L to H
WRITE ABORT (Continue Burst)
INHIBIT CLOCK
Current L to H
Key:
X = Don’t Care, H = HIGH, L = LOW.
BWn = H means all byte write signals (BWa and BWb
) are HIGH.
BW
n = L means one or more byte
write signals are LOW.
Notes:
1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chose in the initial
BEGIN BURST cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first.
2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a
WRITE command is given, but no operation is performed.
3 OE may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE
cycle. OE may be used when the bus turn-on and turn-off times do not meet an application’s requirements.
4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will
remain in High-Z. No WRITE operations will be performed during the INHIBIT CLOCK cycle.
5
BW
a enables WRITEs to byte “a” (DQa pins/balls);
BW
b enables WRITEs to byte “b” (DQb pins/balls).
6 All inputs except
OE
and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
7 Wait states are inserted by setting
CEN
HIGH.
8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE.
10 The address counter is incremented for all CONTINUE BURST cycles.
7/12/04, v. 1.0
Alliance Semiconductor
P. 5 of 14
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
