AS7C33512NTF18A
®
Signal descriptions
Signal
CLK
CEN
A, A0, A1
DQ[a,b]
CE0, CE1,
CE2
ADV/LD
R/W
BW[a,b]
OE
LBO
ZZ
NC
I/O Properties Description
I
I
I
I/O
I
I
I
I
I
I
I
-
CLOCK
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
ASYNC
STATIC
ASYNC
-
Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock.
Clock enable. When de-asserted high, the clock input signal is masked.
Address. Sampled when all chip enables are active and ADV/LD is asserted.
Data. Driven as output when the chip is enabled and OE is active.
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.
Are ignored when ADV/LD is high.
Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO input value. (refer to table on page 2) When low, a new
address is loaded.
A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is high.
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
Asynchronous output enable. I/O pins are not driven when OE is inactive.
Selects Burst mode. When tied to V
DD
or left floating, device follows Interleaved Burst
order. When driven Low, device follows linear Burst order.
This signal is internally pulled
High.
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
No connects. Note that pin 84 will be used for future address expansion to 16Mb density.
Burst Order
Interleaved Burst Order LBO=1
A1 A0 A1 A0 A1 A0 A1 A0
Starting Address
First increment
Second increment
Third increment
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Starting Address
First increment
Second increment
Third increment
Linear Burst Order LBO=0
A1 A0 A1 A0 A1 A0 A1 A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
7/12/04, v. 1.0
Alliance Semiconductor
P. 4 of 14
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
