AS7C331MPFS18A
®
Synchronous truth table
CE0
H
L
L
L
L
L
L
L
L
X
X
X
X
H
H
H
H
L
X
H
X
H
CE1
X
L
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
CE2
X
X
X
H
H
L
L
L
L
X
X
X
X
X
X
X
X
L
X
X
X
X
ADSP
X
L
H
L
H
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
ADSC
L
X
L
X
L
X
X
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
ADV
X
X
X
X
X
X
X
X
X
L
L
H
H
L
L
H
H
X
L
L
H
H
BWn
1
X
X
X
X
X
X
X
F
F
F
F
F
F
F
F
F
F
T
T
T
T
T
OE
X
X
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
X
Address accessed
NA
NA
NA
NA
NA
External
External
External
External
Next
Next
Current
Current
Next
Next
Current
Current
External
Next
Next
Current
Current
CLK
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
Operation
Deselect
Deselect
Deselect
Deselect
Deselect
Begin read
Begin read
Begin read
Begin read
Continue read
Continue read
Suspend read
Suspend read
Continue read
Continue read
Suspend read
Suspend read
Begin write
Continue write
Continue write
Suspend write
Suspend write
DQ
Hi
−
Z
Hi
−
Z
Hi
−
Z
Hi
−
Z
Hi
−
Z
Hi
−
Z
2
Hi
−
Z
Hi
−
2
Hi
−
Z
Q
Hi
−
Z
Q
Hi
−
Z
Q
Hi
−
Z
Q
Hi
−
Z
D
3
D
D
D
D
1
See “Write enable truth table” on page 4 for more information.
2 Q in flow-through mode.
3
For a write operation following a read operation,
OE
must be high before the input data set up time and must be held high throughout the input hold time
Key: X = don’t care, L = low, H = high
TQFP and BGA thermal resistance
Description
Thermal resistance
(junction to ambient)
1
Thermal resistance
(junction to top of case)
1
1
This parameter is sampled.
1 layer
4 layer
Symbol
θ
JA
θ
JA
θ
JC
Typical
40
22
8
Units
°
C/W
°
C/W
°
C/W
Conditions
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA/JESD51
5/28/03, v. 052003 Advance Info
Alliance Semiconductor
5 of 21
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
