May 2003
Advance Information
®
AS7C331MPFS18A
1M x 18 pipelined burst synchronous SRAM
Features
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•
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•
•
•
•
•
Organization: 1,048,576 x18 bits
Fast clock speeds to 200MHz in LVTTL/LVCMOS
Fast clock to data access: 3/3.4/3.8 ns
Fast OE access time: 3/3.4/3.8 ns
Fully synchronous register-to-register operation
Single register flow-through mode
Single-cycle deselect
Asynchronous output enable control
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•
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Available 100-pin TQFP and 165-ball BGA packages
Byte write enables
Multiple chip enables for easy expansion
3.3 V core power supply
2.5 V or 3.3V I/O operation with separate V
DDQ
NTD™ pipelined architecture available (AS7C331MNTD18A,
AS7C33512NTD32A/ AS7C33512NTD36A)
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[19:0]
CLK
CS
CLR
Burst logic
Q
20
D
CS
CLK
20
18 20
Address
register
1M
[
18
Memory
array
18
GWE
BW
b
BWE
BW
a
CE0
CE1
CE2
D
DQb
Q
18
Byte Write
registers
Byte Write
registers
CLK
D
CLK
D
DQa
Q
2
OE
Enable
Q
register
CE
CLK
ZZ
Output
registers
CLK
Input
registers
CLK
Power
down
D
Enable
Q
delay
register
CLK
OE
18
FT DQ[a,b]
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-200
5
200
3.0
370
130
70
-166
6
166
3.4
340
120
70
-133
7.5
133
3.8
320
110
70
Units
ns
MHz
ns
mA
mA
mA
5/28/03, v. 052003 Advance Info
Alliance Semiconductor
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