欢迎访问ic37.com |
会员登录 免费注册
发布采购

AS7C331MFT18A-85TQIN 参数 Datasheet PDF下载

AS7C331MFT18A-85TQIN图片预览
型号: AS7C331MFT18A-85TQIN
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 1MX18, 8.5ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100]
分类和应用: 时钟静态存储器内存集成电路
文件页数/大小: 19 页 / 512 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
 浏览型号AS7C331MFT18A-85TQIN的Datasheet PDF文件第1页浏览型号AS7C331MFT18A-85TQIN的Datasheet PDF文件第2页浏览型号AS7C331MFT18A-85TQIN的Datasheet PDF文件第3页浏览型号AS7C331MFT18A-85TQIN的Datasheet PDF文件第4页浏览型号AS7C331MFT18A-85TQIN的Datasheet PDF文件第6页浏览型号AS7C331MFT18A-85TQIN的Datasheet PDF文件第7页浏览型号AS7C331MFT18A-85TQIN的Datasheet PDF文件第8页浏览型号AS7C331MFT18A-85TQIN的Datasheet PDF文件第9页  
AS7C331MFT18A  
®
Signal descriptions  
Signal I/O Properties  
Description  
CLK  
I
I
CLOCK Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.  
A,A0,A1  
SYNC  
SYNC  
Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.  
Data. Driven as output when the chip is enabled and when OE is active.  
DQ[a,b] I/O  
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is  
inactive, ADSP is blocked. Refer to the “Synchronous truth table” for more information.  
CE0  
I
I
SYNC  
SYNC  
Synchronous chip enables. Active high and active LOW, respectively. Sampled on clock edges  
when ADSC is active or when CE0 and ADSP are active.  
CE1, CE2  
ADSP  
ADSC  
ADV  
I
I
I
SYNC  
SYNC  
SYNC  
Address strobe processor. Asserted LOW to load a new bus address or to enter standby mode.  
Address strobe controller. Asserted LOW to load a new address or to enter standby mode.  
Advance. Asserted LOW to continue burst read/write.  
Global write enable. Asserted LOW to write all 32/36 and 18 bits. When HIGH, BWE and  
BW[a,b] control write enable.  
GWE  
BWE  
I
I
SYNC  
SYNC  
Byte write enable. Asserted LOW with GWE HIGH to enable effect of BW[a,b] inputs.  
Write enables. Used to control write of individual bytes when GWE is HIGH and BWE is  
LOW. If any of BW[a,b] is active with GWE HIGH and BWE LOW, the cycle is a write cycle.  
If all BW[a,b] are inactive, the cycle is a read cycle.  
BW[a,b]  
I
SYNC  
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read  
mode.  
OE  
I
I
ASYNC  
STATIC  
Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When  
driven LOW, device follows linear Burst order. This signal is internally pulled HIGH.  
LBO  
ZZ  
I
-
ASYNC Sleep. Places device in low power mode; data is retained. Connect to GND if unused.  
No connect  
NC  
-
Snooze Mode  
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of  
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.  
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.  
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ is  
disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.  
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting  
SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.  
1/21/05, v 1.4  
Alliance Semiconductor  
5 of 19