December 2002
Advance Information
®
AS7C25512PFS32A
AS7C25512PFS36A
2.5V 512K
×
32/36 pipelined burst synchronous SRAM
Features
•
•
•
•
•
•
•
•
•
•
•
•
Organization: 524,288 words × 32 or 36 bits
Fast clock speeds to 250MHz in LVTTL/LVCMOS
Fast clock to data access: 2.6/2.8/3/3.4 ns
Fast OE access time: 2.6/2.8/3/3.4 ns
Fully synchronous register-to-register operation
Single register flow-through mode
Single-cycle deselect
Asynchronous output enable control
Available in 100-pin TQFP package and 165-ball BGA
Individual byte write and global write
Multiple chip enables for easy expansion
2.5V core power supply
•
•
•
•
•
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
Boundary scan using IEEE 1149.1 JTAG function
NTD™
1
pipelined architecture available
(AS7C251MNTD18A, AS7C25512NTD32A/
AS7C25512NTD36A)
1 NTD™ is a trademark of Alliance Semiconductor Corporation. All trademarks
mentioned in this document are the property of their respective owners.
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[18:0]
19
CLK
CE
CLR
D
CE
Address
register
CLK
D
Q0
Burst logic
Q1
19
Q
17
19
512K × 32/36
Memory
array
GWE
BWE
BW
d
DQ
d
Q
Byte write
registers
CLK
D
DQ
c
Q
Byte write
registers
CLK
DQ
b
Q
Byte write
registers
CLK
D
DQ
Q
a
Byte write
registers
CLK
D
Enable
CE
register
CLK
Power
down
D
Enable
Q
delay
register
CLK
Q
D
36/32
36/32
BW
c
BW
b
BW
a
CE0
CE1
CE2
4
OE
Output
registers
CLK
Input
registers
CLK
ZZ
OE
FT
36/32
DQ[a:d]
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-250
4
250
2.6
450
160
70
-225
4.4
225
2.8
425
150
70
-200
5
200
3.0
400
130
70
-166
6
166
3.4
350
120
70
Units
ns
MHz
ns
mA
mA
mA
12/2/02, v. 0.9.1
Alliance Semiconductor
1 of 21
Copyright © Alliance Semiconductor. All rights reserved.
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
