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IEEE 1149.1 serial boundary scan (JTAG)
The SRAM incorporates a serial boundary scan test access port (TAP). The port operates in accordance with IEEE Standard 1149.1-1990 but
does not have the set of functions required for full 1149.1 compliance. The inclusion of these functions would place an added delay in the
critical speed path of the SRAM. The TAP controller functionality does not conflict with the operation of other devices using 1149.1 fully
compliant TAPs. It uses JEDEC-standard 2.5V I/O logic levels.
The SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.
Disabling the JTAG feature
If the JTAG function is not being implemented, its pins/balls can be left unconnected. At power-up, the device will come up in a reset state
which will not interfere with the operation of the device.
TAP controller state diagram
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TAP controller block diagram
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Test access port (TAP)
Test clock (TCK)
The test clock is used with only the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling
edge of TCK.
Test mode select (TMS)
The TAP controller receives commands from TMS input. It is sampled on the rising edge of TCK. You can leave this pin/ball unconnected if the
TAP is not used. The pin/ball is pulled up internally, resulting in a logic high level.
12/2/02, v. 0.9.1
Alliance Semiconductor
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ISSI [ INTEGRATED SILICON SOLUTION, INC ]
