AS7C25512PFS32A
AS7C25512PFS36A
®
Timing characteristics over operating range
–250
Parameter
Clock frequency
Cycle time (pipelined mode)
Cycle time (flow-through mode)
Clock access time (pipelined mode)
Clock access time (flow-through
mode)
Output enable low to data valid
Clock high to output low Z
Data output invalid from clock high
Output enable low to output low Z
Output enable high to output high Z
Clock high to output high Z
Output enable high to invalid output
Clock high pulse width
Clock low pulse width
Address setup to clock high
Data setup to clock high
Write setup to clock high
Chip select setup to clock high
Address hold from clock high
Data hold from clock high
Write hold from clock high
Chip select hold from clock high
ADV setup to clock high
ADSP setup to clock high
ADSC setup to clock high
ADV hold from clock high
ADSP hold from clock high
ADSC hold from clock high
1
–225
Min
–
4.4
6.9
–
–
–
0
1.5
0
–
–
0
1.8
1.8
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
1.4
1.4
1.4
0.4
0.4
0.4
Max
225
–
–
2.8
6.9
2.8
–
–
–
2.8
2.8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
5
–200
Min
Max
200
–
–
3.0
7.5
3.0
–
–
–
3.0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
6
–166
Min
Max
166
–
–
3.4
8.5
3.4
–
–
–
3.4
3.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
6
6
6,7
6,8
6
6
6,7
6,8
6
6
6
6
6
6
2,3,4
2
2,3,4
2,3,4
2,3,4
Notes
1
Sym
f
Max
t
CYC
t
CYCF
t
CD
t
CDF
t
OE
t
LZC
t
OH
t
LZOE
t
HZOE
t
HZC
t
OHOE
t
CH
t
CL
t
AS
t
DS
t
WS
t
CSS
t
AH
t
DH
t
WH
t
CSH
t
ADVS
t
ADSPS
t
ADSCS
t
ADVH
t
ADSPH
t
ADSCH
Min
–
4
6.5
–
–
–
0
1.5
0
–
–
0
1.5
1.5
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
1.2
1.2
1.2
0.3
0.3
0.3
Max
250
–
–
2.6
6.5
2.6
–
–
–
2.6
2.6
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
7.5
–
–
–
0
1.5
0
–
–
0
1.8
1.8
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
1.4
1.4
1.4
0.4
0.4
0.4
8.5
–
–
–
0
1.5
0
–
–
0
2.1
2.2
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
12/2/02, v. 0.9.1
Alliance Semiconductor
8 of 21
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
