®
IS61LV5128
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-10 ns
Min.
-12 ns
Min.
-15 ns
Min. Max.
Symbol
tWC
Parameter
Max.
—
Max.
—
Unit
ns
Write Cycle Time
CE to Write End
Address Setup Time to
10
8
12
9
15
10
10
—
—
—
tSCE
—
—
ns
tAW
8
—
9
—
ns
Write End
tHA
Address Hold from
0
—
0
—
0
—
ns
Write End
tSA
Address Setup Time
0
8
—
—
—
—
—
5
0
8
—
—
—
—
—
6
0
10
12
7
—
—
—
—
—
7
ns
ns
ns
ns
ns
ns
ns
tPWE1(4)
tPWE2
tSD
WE Pulse Width
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
10
6
12
6
tHD
0
0
0
(2)
tHZWE
0
0
0
(2)
tLZWE
0
—
0
—
0
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
outputloadingspecifiedinFigure1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
t
SA
t
t
HA
t
AW
t
tPPWWEE21
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
D
IN
CE_WR1.eps
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. B
07/16/01
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
