IS61NLP12832B
IS61NLP12836B/IS61NVP12836B
IS61NLP25618A/IS61NVP25618A
PIN CONFIGURATION
100-Pin TQFP
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
NC
V
DDQ
Vss
VDDQ
Vss
NC
NC
NC
DQPa
DQb
DQb
Vss
DQa
DQa
Vss
V
DDQ
VDDQ
DQb
DQa
DQb
NC
DQa
Vss
NC
VDD
NC
Vss
VDD
ZZ
DQb
DQb
DQa
DQa
V
DDQ
VDDQ
Vss
DQb
Vss
DQa
DQa
DQb
DQPb
NC
NC
NC
Vss
Vss
V
DDQ
VDDQ
NC
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
256K x 18
PIN DESCRIPTIONS
A0,ꢀA1ꢀ
SynchronousꢀAddressꢀInputs.ꢀTheseꢀ
pinsꢀmustꢀtiedꢀtoꢀtheꢀtwoꢀLSBsꢀofꢀtheꢀ
address bus.
CE, CE2, CE2 Synchronous Chip Enable
OE
Output Enable
DQa-DQdꢀ
SynchronousꢀDataꢀInput/Output
A
Synchronous Address Inputs
SynchronousꢀClock
DQPa-DQPdꢀ ParityꢀDataꢀI/O
MODEꢀꢀ ꢀ BurstꢀSequenceꢀSelection
CLKꢀꢀ
ADVꢀꢀ
BWa-BWdꢀ
WEꢀ
SynchronousꢀBurstꢀAddressꢀAdvance
SynchronousꢀByteꢀWriteꢀEnable
WriteꢀEnable
Vd d ꢀ
VS S ꢀ
Vd d q
ZZꢀ
ꢀ
ꢀ
+3.3V/2.5VꢀPowerꢀSupply
GroundꢀforꢀoutputꢀBuffer
IsolatedꢀOutputꢀBufferꢀSupply:ꢀ+3.3V/2.5V
SnoozeꢀEnable
CKE
Clock Enable
ꢀ
Vssꢀ
NCꢀ
ꢀ
ꢀ
GroundꢀforꢀCore
NotꢀConnected
Integrated Silicon Solution, Inc. — www.issi.com
9
Rev. D
09/10/07
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
