IR2166
Ballast Design Equations
to increase in order to keep the DC bus constant.
Should the on-time increase too far, the resulting
peak currents in LPFC can exceed the saturation
current limit of LPFC. LPFC will then saturate
and very high peak currents and di/dt levels will
occur. To prevent this, the maximum on-time is
limited by limiting the maximum voltage on the
COMP pin with an external zener diode DCOMP
(Figure 8). As the line input voltage decreases,
the COMP pin voltage and therefore the on-time
will eventually limit. The PFC can no longer
supply enough current to keep the DC bus fixed
for the given load power and the DC bus will
begin to drop. Decreasing the line input voltage
further will cause the VBUS pin to eventually
decrease below the internal 3V threshold (Figure
9). When this occurs, VCC is discharged
internally to UVLO-, the IR2166 enters UVLO
mode and both the PFC and ballast sections
are disabled (see State Diagram). The start-up
supply resistor to VCC, together with the micro-
power start-up current of the IR2166, determine
the line input turn-on voltage. This should be
set such that the ballast turns on at a line voltage
level above the under-voltage turn-off level. It
is the correct selection of the value of the supply
resistor to VCC and the zener diode on the
COMP pin that correctly program the on and off
line input voltage thresholds for the ballast. With
these thresholds correctly set, the ballast will
turn off due to the 3V under-voltage threshold
on the VBUS pin, and on again at a higher line
input voltage (hysterisis) due to the supply
resistor to VCC. This hysterisis will result in a
proper reset of the ballast without flickering of
the lamp, bouncing of the DC bus or re-ignition
of the lamp when the DC bus is too low.
Note: The results from the following design
equations can differ slightly from experimental
measurements due to IC tolerances, component
tolerances, and oscillator over- and undershoot
due to internal comparator response time.
Step 1: Program Dead-time
The dead-time between the gate driver outputs
HO and LO is programmed with timing capacitor
CT and an internal dead-time resistor RDT. The
dead-time is the discharge time of capacitor CT
from 3/5VCC to 1/3VCC and is given as:
[Seconds]
(1)
tDT = CT 1475
or
tDT
CT =
[Farads]
(2)
1475
Step 2: Program Run Frequency
The final run frequency is programmed with
timing resistor RT and timing capacitor CT. The
charge time of capacitor CT from 1/3VCC to
3/5VCC determines the on-time of HO and LO
gate driver outputs. The run frequency is
therefore given as:
1
fRUN
=
[Hertz] (3)
2 CT (0.51 RT +1475)
or
1
RT =
− 2892
[Ohms] (4)
1.02 CT fRUN
26
www.irf.com
INFINEON [ Infineon ]
