IR2166
II. PFC Section Functional Description
lower than the minimum specified ballast input
voltage. This hysteresis will result in clean turn-
on and turnoff of the ballast.
In most electronic ballasts it is necessary to
have the circuit act as a pure resistive load to
the AC input line voltage. The degree to which
the circuit matches a pure resistor is measured
by the phase shift between the input voltage
and input current and how well the shape of the
input current waveform matches the shape of
the sinusoidal input voltage. The cosine of the
phase angle between the input voltage and input
current is defined as the power factor (PF), and
how well the shape of the input current waveform
matches the shape of the input voltage is
determined by the total harmonic distortion
(THD). A power factor of 1.0 (maximum)
corresponds to zero phase shift and a THD of
0% represents a pure sinewave (no distortion).
For this reason it is desirable to have a high PF
and a low THD. To achieve this, the IR2166
includes an active power factor correction (PFC)
circuit which, for an AC line input voltage,
produces an AC line input current. The control
method implemented in the IR2166 is for a boost-
type converter (Figure 6) running in critical-
conduction mode (CCM). This means that during
each switching cycle of the PFC MOSFET, the
circuit waits until the inductor current discharges
to zero before turning the PFC MOSFET on again.
The PFC MOSFET is turned on and off at a
much higher frequency (>10KHz) than the line
input frequency (50 to 60Hz).
CS and EOL Fault Mode (FAULT)
Should the voltage at the SD/EOL pin exceed 3V
or decrease below 1V during RUN mode, the IC
enters fault mode and all gate driver outputs, HO,
LO and PFC, are latched off in the 'low' state.
CPH is discharged to COM for resetting the
preheat time, and CT is discharged to COM for
disabling the oscillator. To exit fault mode, VCC
must be recycled back below the UVLO negative-
going turn-off threshold, or, the shutdown pin, SD,
must be pulled above 5.2 volts. Either of these
will force the IC to enter UVLO mode (see State
Diagram, page 7). Once VCC is above the turn-
on threshold and SD is below 5.0 volts, the IC
will begin oscillating again in the preheat mode.
The current sense function will force the IC to
enter FAULT mode only after the voltage at the
current sense pin has been pulsed about 25 times
with a voltage greater than 1.3 volts during preheat
and ignition modes only. These over-currents must
occur during the on-time of LO. During run mode,
a single pulse on the CS pin above 1.3V will force
the IC to enter FAULT mode.
25 Pulses
LO
DPFC
LPFC
DC Bus
(+)
CS
2.0V
+
CBUS
MPFC
(-)
Run Mode
Fault Mode
Figure 6: Boost-type PFC circuit
Figure 5: FAULT counter during preheat and ignition
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