IR2166
modulation circuit has been added to the PFC
control. This circuit dynamically increases the
on-time of MPFC as the line input voltage nears
the zero-crossings (Figure 11). This causes the
peak LPFC current, and therefore the smoothed
line input current, to increase slightly higher near
the zero-crossings of the line input voltage. This
reduces the amount of cross-over distortion in
the line input current which reduces the THD
and higher harmonics to low levels.
ILPFC
0
0
0
PFC
pin
ILPFC
0
ZX
pin
PFC
pin
0
near peak region of
rectified AC line
near zero-crossing region
of rectified AC line
Figure 10: LPFC current, PFC pin and ZX pin timing
diagram.
Figure 11: On-time modulation near the zero-crossings.
Over-voltage Protection (OVP)
On-time Modulation
Should over-voltage occur on the DC bus
causing the VBUS pin to exceed the internal 4.3V
threshold, the PFC output is disabled (set to a
logic 'low'). When the DC bus decreases again
causing the VBUS pin to decrease below the
internal 4V threshold, a watch-dog pulse is forced
on the PFC pin and normal PFC operation is
resumed.
A fixed on-time of MPFC over an entire cycle of
the line input voltage produces a peak inductor
current which naturally follows the sinusoidal
shape of the line input voltage. The smoothed
averaged line input current is in phase with the
line input voltage for high power factor but the
total harmonic distortion (THD), as well as the
individual higher harmonics, of the current can
still be too high. This is mostly due to cross-
over distortion of the line current near the zero-
crossings of the line input voltage. To achieve
low harmonics which are acceptable to
international standard organizations and general
market requirements, an additional on-time
Under-voltage Reset (UVR)
When the line input voltage is decreased,
interrupted or a brown-out condition occurs, the
PFC feedback loop causes the on-time of MPFC
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