IR2166
Ignition Mode (IGN)
RT and timing capacitor CT (see Design
Equations, page 26, Equations 3 and 4). Should
The ignition mode is defined as the state the IC hard-switching occur at the half-bridge at any
is in when a high voltage is being established time due to an open-filament or lamp removal,
across the lamp necessary for igniting the lamp. the voltage across the current sensing resistor,
The IR2166 enters ignition mode when the RCS, will exceed the internal threshold of 1.3 volts
voltage on pin CPH exceeds 10V.
and the IC will enter FAULT mode and gate driver
outputs HO, LO and PFC will be latched low.
Pin CPH is connected internally to the gate of a
P-channel MOSFET (S4) (see Figure 4) that DC Bus Under-voltage Reset
connects pin RPH with pin RT. As pin CPH
exceeds 10V, the gate-to-source voltage of Should the DC bus decrease too low during a
MOSFET S4 begins to fall below the turn-on brownout line condition or overload condition,
threshold of S4. As pin CPH continues to ramp the resonant output stage to the lamp can shift
towards VCC, switch S4 turns off slowly. This near or below resonance. This can produce
results in resistor RPH being disconnected hard-switching at the half-bridge which can
smoothly from resistor RT, which causes the damage the half-bridge switches or, the DC bus
operating frequency to ramp smoothly from the can decrease too far and the lamp can
preheat frequency, through the ignition frequency, extinguish. To protect against this, the VBUS pin
to the final run frequency. The over-current includes a 3.0V under-voltage threshold. Should
threshold on pin CS will protect the ballast the voltage at the VBUS pin decrease below 3.0V,
against a non-strike or open-filament lamp fault VCC will be discharged to the UVLO- threshold
condition. The voltage on pin CS is defined by and all gate driver outputs will be latched low.
the lower half-bridge MOSFET current flowing
through the external current sensing resistor For proper ballast design, the designer should
RCS. The resistor RCS therefore programs the design the PFC section such that the DC bus
maximum allowable peak ignition current (and does not drop until the AC line input voltage falls
therefore peak ignition voltage) of the ballast below the rated input voltage of the ballast (See
output stage. If the number of over current pulses PFC section). When correctly designed, the
exceed 25, the IC will enter fault mode and gate voltage measured at the VBUS pin will decrease
driver outputs HO, LO and PFC will be latched below the internal 3.0V threshold and the ballast
low.
will turn off cleanly. The pull-up resistor to VCC
( SUPPLY) will then turn the ballast on again
R
Run Mode (RUN)
with the AC input line voltage increasing to the
minimum specified value causing VCC to exceed
UVLO+.
Once the lamp has successfully ignited, the
ballast enters run mode. The run mode is defined
as the state the IC is in when the lamp arc is
established and the lamp is being driven to a
given power level. The run mode oscillating
frequency is determined by the timing resistor
R
SUPPLY should be set to turn the ballast on at
the minimum specified ballast input voltage. The
PFC should then be designed such that the DC
bus decreases at an input line voltage that is
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