HIP6016
LUV
OC1
FAULT
REPORTED
OVER
CURRENT
LATCH
INHIBIT
10V
0V
S
Q
COUNT
= 1
COUNT
= 2
COUNT
= 3
S
R
0.15V
+
-
4V
2V
0V
COUNTER
FAULT
LATCH
VCC
R
S
Q
UP
SS
OV
+
-
4V
R
POR
OVERLOAD
APPLIED
FAULT
FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC
latch. A sequence of three over-current fault signals also
0A
sets the fault latch. A comparator indicates when C is fully
SS
charged (UP signal), such that an under-voltage event on
either linear output (VSEN2 or VSEN3) is ignored until after
the soft-start interval (T4 in Figure 6). At start-up, this allows
t0 t1
t2
t3
t4
TIME
FIGURE 8. OVER-CURRENT OPERATION
V
and V to slew up over increased time intervals.
OUT2
OUT3
Cycling the bias input voltage (+12V on the VCC pin) off
IN
then on resets the counter and the fault latch.
soft-start voltage continues increasing to 4V before
discharging. The counter increments to 2. The soft-start cycle
repeats at T3 and trips the over-current comparator. The SS
pin voltage increases to 4V at T4 and the counter increments
to 3. This sets the fault latch to disable the converter. The fault
is reported on the FAULT pin.
Over-Voltage Protection
During operation, a short on the upper PWM MOSFET (Q1)
causes V
to increase. When the output exceeds the
OUT1
over-voltage threshold of 115% (typical) of DACOUT, the
over-voltage comparator trips to set the fault latch and turns
The linear regulator operates in the same way as PWM to
over-current faults. Additionally, the linear regulator and
linear controller monitor the feedback pins for an under-
voltage. Should excessive currents cause VSEN2 or VSEN3
to fall below the linear under-voltage threshold, the LUV
Q2 on. This blows the input fuse and reduces V
fault latch raises the FAULT pin close to VCC potential.
. The
OUT1
A separate over-voltage circuit provides protection during
the initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), V
is
OUT1
signal sets the over-current latch if C is fully charged.
SS
monitored for voltages exceeding 1.26V. Should VSEN1
exceed this level, the lower MOSFET (Q2) is driven on.
Blanking the LUV signal during the C charge interval allows
SS
the linear outputs to build above the under-voltage threshold
during normal start-up. Cycling the bias input power off then
on resets the counter and the fault latch.
Over-Current Protection
All outputs are protected against excessive over-currents. The
PWM controller uses the upper MOSFET’s on-resistance,
V
> V
SET
)
OVER-CURRENT TRIP:
DS
OCSET
V
= +5V
r
to monitor the current for protection against shorted
IN
DS(ON)
(i • r > I • R
D
DS(ON)
OCSET
outputs. The linear regulator monitors the current of the
integrated power device and signals an over-current condition
for currents in excess of 180mA. Additionally, both the linear
regulator and the linear controller monitor VSEN2 and VSEN3
for under-voltage to protect against excessive currents.
R
OCSET
OCSET
I
i
OCSET
200µA
+
D
V
SET
VCC
+
UGATE
PHASE
DRIVE
Figures 8 and 9 illustrate the over-current protection with an
overload on OUT1. The overload is applied at T0 and the
V
DS
OC1
OVER-
+
-
current increases through the output inductor (L
). At time
OUT1
T1, the OVER-CURRENT1 comparator trips when the voltage
across Q1 (I • r ) exceeds the level programmed by
VCC
CURRENT1
V
= V - V
IN
PHASE
DS
D
DS(ON)
LGATE
PGND
PWM
GATE
CONTROL
V
= V - V
IN
OCSET
SET
R
. This inhibits all outputs, discharges the soft-start
OCSET
capacitor (C ) with a 11µA current sink, and increments the
HIP6016
SS
counter. C recharges at T2 and initiates a soft-start cycle
SS
with the error amplifiers clamped by soft-start. With OUT1 still
overloaded, the inductor current increases to trip the over-
current comparator. Again, this inhibits all outputs, but the
FIGURE 9. OVER-CURRENT DETECTION
2-203
INTERSIL [ Intersil ]
