HIP6016
shown in Figure 12. Using the above guidelines should yield a
V
IN
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
OSC
DRIVER
DRIVER
PWM
L
O
V
OUT
compensation gain at F with the capabilities of the error
COMP
P2
∆V
OSC
-
amplifier. The closed loop gain is constructed on the log-log
graph of Figure 12 by adding the modulator gain (in dB) to the
compensation gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.
PHASE
+
C
O
ESR
(PARASITIC)
Z
FB
V
E/A
Z
-
IN
+
100
ERROR
AMP
F
F
F
P1
F
Z1
Z2
P2
REFERENCE
80
60
40
20
0
OPEN LOOP
ERROR AMP GAIN
DETAILED FEEDBACK COMPENSATION
Z
FB
V
OUT
C2
R2
20LOG
(R /R )
Z
IN
2
1
20LOG
C1
C3
R3
(V /∆V
)
IN OSC
MODULATOR
GAIN
COMPENSATION
GAIN
R1
-20
-40
-60
COMP
CLOSED LOOP
GAIN
-
+
F
FB
LC
F
ESR
100K
FREQUENCY (Hz)
10
100
1K
10K
1M
10M
HIP6016
REFERENCE
FIGURE 12. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
FIGURE 11. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The compensation gain uses external impedance networks
Z
and Z to provide a stable, high bandwidth loop. A stable
a closed loop transfer function with an acceptable 0dB
crossing frequency (f ) and adequate phase margin.
FB
IN
control loop has a 0dB gain crossing with -20dB/decade slope
and a phase margin greater than 45 degrees. Include worst
case component variations when determining phase margin.
0dB
Phase margin is the difference between the closed loop
phase at f and 180 degrees. The equations below relate
0dB
the compensation network’s poles, zeros and gain to the
components (R1, R2, R3, C1, C2, and C3) in Figure 11.
Use these guidelines for locating the poles and zeros of the
compensation network:
Component Selection Guidelines
Output Capacitor Selection
The output capacitors for each output have unique
requirements. In general the output capacitors should be
selected to meet the dynamic regulation requirements.
Additionally, the PWM converters require an output capacitor
to filter the current ripple. The linear regulator is internally
compensated and requires an output capacitor that meets
the stability requirements. The load transient for the
microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.
1. Pick Gain (R2/R1) for desired converter bandwidth
ST
2. Place 1 Zero Below Filter’s Double Pole (~75% FLC)
ND
3. Place 2
Zero at Filter’s Double Pole
ST
4. Place 1 Pole at the ESR Zero
ND
5. Place 2
Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if necessary
Compensation Break Frequency Equations
PWM Output Capacitors
Modern microprocessors produce transient load rates above
10A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and ESL (effective series
inductance) parameters rather than actual capacitance.
1
1
F
= -------------------------------------------------------
F
= -----------------------------------
2π × R2 × C1
P1
Z1
C1 × C2
2π × R
×
----------------------
2
C1 + C2
1
1
F
= -----------------------------------
F
= -------------------------------------------------------
2π × (R1 + R3) × C3
P2
Z2
2π × R3 × C3
Figure 12 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual modulator gain has a peak due
to the high Q factor of the output filter at F , which is not
LC
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
2-206
INTERSIL [ Intersil ]
