HIP6016
voltage reach the valley of the oscillator’s triangle wave. The
VIN2 (Pin 12)
oscillator’s triangular waveform is compared to the clamped
error amplifier output voltage. As the SS pin voltage increases,
the pulse-width on the PHASE pin increases. The interval of
increasing pulse-width continues until each output reaches
sufficient voltage to transfer control to the input reference
This pin supplies power to the internal regulator. Connect
this pin to a suitable 3.3V source.
Additionally, this pin is used to monitor the 3.3V supply. If,
following a start-up cycle, the voltage drops below 2.45V
(typically), the chip shuts down. A new soft-start cycle is
initiated upon return of the 3.3V supply above the under-
voltage threshold.
clamp. If we consider the 2.0V output (V
) in Figure 6, this
OUT1
time occurs at T2. During the interval between T2 and T3, the
error amplifier reference ramps to the final value and the
converter regulates the output to a voltage proportional to the
SS pin voltage. At T3 the input clamp voltage exceeds the
reference voltage and the output voltage is in regulation.
Description
Operation
The HIP6016 monitors and precisely controls 3 output
voltage levels (Refer to Figures 1, 2, and 3). It is designed for
microprocessor computer applications with 3.3V and 5V
power, and 12V bias input from an ATX power supply. The IC
has one PWM controller, a linear controller, and a linear
regulator. The PWM controller is designed to regulate the
PGOOD
(1V/DIV)
0V
microprocessor core voltage (V
) by driving 2 MOSFETs
OUT1
(Q1 and Q2) in a synchronous-rectified buck converter
configuration. The core voltage is regulated to a level
programmed by the 5-bit digital-to-analog converter (DAC).
An integrated linear regulator supplies the 2.5V clock power
SOFT-START
(1V/DIV)
(V
). The linear controller drives an external MOSFET
OUT2
0V
(Q3) to supply the 1.5V GTL bus power (V
).
V
( = 2.5V)
OUT3
OUT2
Initialization
V
(DAC = 2V)
OUT1
The HIP6016 automatically initializes upon receipt of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input supply voltages. The POR monitors the bias
V
( = 1.5V)
OUT3
OUTPUT
VOLTAGES
(0.5V/DIV)
voltage (+12V ) at the VCC pin, the 5V input voltage (+5V )
IN IN
on the OCSET pin, and the 3.3V input voltage (+3.3V ) on the
IN
0V
VIN2 pin. The normal level on OCSET is equal to +5V less a
IN
fixed voltage drop (see over-current protection). The POR
function initiates soft-start operation after all three input supply
voltages exceed their POR thresholds.
T0 T1
T2
T3
T4
TIME
FIGURE 6. SOFT-START INTERVAL
Soft-Start
The POR function initiates the soft-start sequence. Initially, the
voltage on the SS pin rapidly increases to approximately 1V
(this minimizes the soft-start interval). Then an internal 11µA
The remaining outputs are also programmed to follow the SS
pin voltage. Each linear output (V and V ) initially
OUT2 OUT3
current source charges an external capacitor (C ) on the SS
follows a ramp similar to that of the PWM output. When each
output reaches sufficient voltage the input reference clamp
slows the rate of output voltage rise. The PGOOD signal
toggles ‘high’ when all output voltage levels have exceeded
their under-voltage levels. See the Soft-Start Interval section
under Applications Guidelines for a procedure to determine
the soft-start interval.
SS
pin to 4V. The PWM error amplifier reference input (+ terminal)
and output (COMP pin) is clamped to a level proportional to the
SS pin voltage. As the SS pin voltage slews from 1V to 4V, the
output clamp generates PHASE pulses of increasing width that
charge the output capacitor(s). After this initial stage, the
reference input clamp slows the output voltage rate-of-rise and
provides a smooth transition to the final set voltage. Additionally
both linear regulator’s reference inputs are clamped to a voltage
proportional to the SS pin voltage. This method provides a
rapid and controlled output voltage rise.
Fault Protection
All three outputs are monitored and protected against
extreme overload. A sustained overload on any linear
regulator output or an over-voltage on the PWM output
disables all converters and drives the FAULT pin to VCC.
Figure 6 shows the soft-start sequence for the typical
application. At T0 the SS voltage rapidly increases to
approximately 1V. At T1, the SS pin and error amplifier output
Figure 7 shows a simplified schematic of the fault logic. An
over-voltage detected on VSEN1 immediately sets the fault
2-202
INTERSIL [ Intersil ]
