HI2555, CXD2555
Timing Diagram
tzd
tds
tdz
SOUT
BCK
tsus
ths
SIN
LRCK
(SLAVE MODE)
tsul
tdl
thl
BCK
LRCK
(MASTER MODE)
twl
XTLI
FIGURE 36.
Description of Functions
TABLE 2.
Serial Data Interface
MLSL
(Related Pins) LRCK, BCK, SOUT, SIN, MASL, MLSL
L
LSB first
The serial data format is common for both SIN (DA converter
input) and SOUT (AD converter output), consisting of two
channels per sampling serial data represented by 2’s com-
plement. Each channel is divided into 32-bit slots, of which
16 bits are handled as data.
MASL is used to select whether the 16 bits of valid data is
placed in the first or the second half of the 32-bit slots.
TABLE 1.
MASL
H
L
Forward Packing
Rearward Packing
Similarly, MLSL is used to select whether the serial data is
arranged at LSB first or MSB first.
TABLE 2.
MLSL
H
MSB first
4-307
INTERSIL [ Intersil ]
