CD4029BMS
Timing Diagrams (Continued)
CLOCK (CL)
CARRY IN
(CL ENABLE)
UP/DOWN
BINARY/
DECADE
PRESET
ENABLE
J1
J2
J3
J4
Q1
Q2
Q3
Q4
CARRY OUT
0
1
2
3
4
5
6
7
8
9
8
7
6
5
4
3
2
1
0
0
9
8
7
COUNT
FIGURE 12. TIMING DIAGRAM-DECADE MODE
“PARALLEL CLOCKING”
UP/DOWN
PRESET
ENABLE
UP/D PE J1 J2 J3 J4
UP/D PE J1 J2 J3 J4
UP/D PE J1 J2 J3 J4
*
CI
CD4029
CO
CI
CD4029
CO
CI
CD4029
CO
B/D CL Q1 Q2 Q3 Q4
B/D CL Q1 Q2 Q3 Q4
B/D CL Q1 Q2 Q3 Q4
CLOCK
BINARY/
DECADE
*CARRY OUT LINES AT THE 2ND, 3RD, ETC, STAGES MAY HAVE A NEG-
ATIVE-GOING GLITCH PULSE RESULTING FROM DIFFERENTIAL
DELAYS OF DIFFERENT CD4029BMS IC’S. THESE NEGATIVE GOING
GLITCHES DO NOT AFFECT PROPER CD4029BMS OPERATION. HOW-
EVER, IF THE CARRY OUT SIGNALS ARE USED TO TRIGGER OTHER
EDGE-SENSITIVE LOGIC DEVICES, SUCH AS FF’S OR COUNTERS, THE
CARRY OUT SIGNALS SHOULD BE GATED WITH THE CLOCK SIGNAL
USING A 2-INPUT OR GATE SUCH AS CD4071BMS.
FIGURE 13. CASCADING COUNTER PACKAGES
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