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CD4027 参数 Datasheet PDF下载

CD4027图片预览
型号: CD4027
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS双J-K·主从触发器 [CMOS Dual J-K Master-Slave Flip-Flop]
分类和应用: 触发器
文件页数/大小: 8 页 / 75 K
品牌: INTERSIL [ Intersil ]
 浏览型号CD4027的Datasheet PDF文件第1页浏览型号CD4027的Datasheet PDF文件第2页浏览型号CD4027的Datasheet PDF文件第3页浏览型号CD4027的Datasheet PDF文件第5页浏览型号CD4027的Datasheet PDF文件第6页浏览型号CD4027的Datasheet PDF文件第7页浏览型号CD4027的Datasheet PDF文件第8页  
Specifications CD4027BMS  
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)  
LIMITS  
MIN  
PARAMETER  
SYMBOL  
CONDITIONS  
NOTES  
TEMPERATURE  
MAX  
-2.4  
-4.2  
3
UNITS  
mA  
o
Output Current (Source)  
IOH15  
VDD =15V, VOUT = 13.5V  
1, 2  
+125 C  
-
-
-
o
-55 C  
mA  
o
o
Input Voltage Low  
Input Voltage High  
VIL  
VDD = 10V, VOH > 9V, VOL < 1V  
VDD = 10V, VOH > 9V, VOL < 1V  
1, 2  
1, 2  
+25 C, +125 C,  
V
o
-55 C  
o
o
VIH  
+25 C, +125 C,  
7
-
V
o
-55 C  
o
Propagation Delay  
Clock To Q, Q  
TPHL1 VDD = 10V  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
+25 C  
-
-
130  
90  
ns  
ns  
TPLH1  
o
VDD = 15V  
+25 C  
o
Propagation Delay  
Set To Q, Reset To Q  
TPLH2 VDD = 10V  
VDD = 15V  
+25 C  
-
130  
90  
ns  
o
+25 C  
-
ns  
o
Propagation Delay  
Set To Q, Reset To Q  
TPHL3 VDD = 10V  
VDD = 15V  
+25 C  
-
170  
120  
100  
80  
ns  
o
+25 C  
-
ns  
o
Transition Time  
TTHL  
TTLH  
VDD = 10V  
VDD = 15V  
VDD = 10V  
VDD = 15V  
+25 C  
-
ns  
o
+25 C  
-
ns  
o
Maximum Clock Input  
Frequency Toggle Mode  
Input TR, TF = 5ns  
FCL  
+25 C  
8
12  
-
MHz  
MHz  
o
+25 C  
-
o
Minimum Data Setup  
Time  
TS  
VDD = 5V  
VDD = 10V  
VDD = 15V  
VDD = 5V  
VDD = 10V  
VDD = 15V  
VDD = 5V  
VDD = 10V  
VDD = 15V  
VDD = 5V  
VDD = 10V  
VDD = 15V  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3  
1, 2, 3, 4  
1, 2, 3, 4  
1, 2, 3, 4  
1, 2  
+25 C  
-
-
-
-
-
-
-
-
-
-
-
-
-
200  
75  
50  
180  
80  
50  
140  
60  
40  
45  
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
µs  
µs  
pF  
o
+25 C  
o
+25 C  
o
Minimum Set or Reset  
Pulse Width  
TW  
TW  
+25 C  
o
+25 C  
o
+25 C  
o
Minimum Clock Pulse  
Width  
+25 C  
o
+25 C  
o
+25 C  
o
Clock Input Rise Or Fall  
Time (Note 5)  
TRCL  
TFCL  
+25 C  
o
+25 C  
o
+25 C  
2
o
Input Capacitance  
NOTES:  
CIN  
+25 C  
7.5  
1. All voltages referenced to device GND.  
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized  
on initial design release and upon design changes which would affect these characteristics.  
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.  
4. If more than one unit is cascaded in a parallel clocked operation, trCL should be made less than or equal to the sum of the fixed propa-  
gation delay time at 15pF and the transition time of the output driving stage for the estimated capacitive load.  
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS  
LIMITS  
PARAMETER  
Supply Current  
SYMBOL  
CONDITIONS  
NOTES  
TEMPERATURE  
MIN  
MAX  
UNITS  
o
IDD  
VDD = 20V, VIN = VDD or GND  
1, 4  
+25 C  
-
7.5  
µA  
7-783  
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