ISL705AEH, ISL705BEH, ISL705CEH, ISL706AEH, ISL706BEH, ISL706CEH
Pin Configurations
ISL705AEH, ISL706AEH
(8 LD FLATPACK)
TOP VIEW
MR
V
DD
GND
PFI
1
2
3
4
8
7
6
5
WDO
RST
WDI
PFO
ISL705BEH, ISL706BEH
(8 LD FLATPACK)
TOP VIEW
MR
V
DD
GND
PFI
1
2
3
4
8
7
6
5
WDO
RST
WDI
PFO
ISL705CEH, ISL706CEH
(8 LD FLATPACK)
TOP VIEW
MR
V
DD
GND
PFI
1
2
3
4
8
7
6
5
WDO
RST_OD
WDI
PFO
Pin Descriptions
ISL705AEH
ISL706AEH
1
2
ISL705BEH
ISL706BEH
1
2
ISL705CEH
ISL706CEH
1
2
NAME
MR
VDD
DESCRIPTION
Manual Reset. MR is an active-low, debounced, TTL/CMOS compatible input that may
be used to trigger a reset pulse.
Power Supply. V
DD
is a supply voltage input that provides power to all internal circuitry.
This input is also monitored and used to trigger a reset pulse. Reset is guaranteed
operable after V
DD
rises above 1.2V.
Ground. GND is a supply voltage return for all internal circuitry. This return establishes
the reference level for voltage detection and should be connected to signal ground.
Power Fail Input. PFI is an input to a threshold detector, which may be used to monitor
another supply voltage level. The threshold of the detector (V
PFI
) is 1.25V in the
ISL705AEH/BEH/CEH and 0.6V in the ISL706AEH/BEH/CEH.
Power Fail Output. PFO is an active-low, push-pull output of a threshold detector that
indicates the voltage at the PFI pin is less than V
PFI
.
Watchdog Input. WDI is a tri-state input that monitors microprocessor activity. If the
microprocessor does not toggle WDI within 1.6s and WDI is not tri-stated, WDO goes
low. As long as reset is asserted or WDI is tri-stated, the watchdog timer will stay cleared
and will not count. As soon as reset is released and WDI is driven high or low, the timer
will start counting. Floating WDI or connecting WDI to a high impedance tri-state buffer
disables the watchdog feature.
Reset. RST is an active-low, push-pull output that is guaranteed to be low once V
DD
reaches 1.2V. As V
DD
rises, RST stays low. When V
DD
rises above a 4.65V
(ISL705AEH/BEH/CEH) or 3.08V (ISL706AEH/BEH/CEH) reset threshold, an internal
timer releases RST after about 200ms. RST pulses low whenever V
DD
goes below the
reset threshold. If a brownout condition occurs in the middle of a previously initiated
reset pulse, the pulse will continue for at least 140ms. On power-down, once V
DD
falls
below the reset threshold, RST goes low and is guaranteed low until V
DD
drops below
1.2V.
Reset. RST is an active-high, push-pull output. RST is the inverse of RST.
Reset. RST_OD is an active-low, open-drain output that goes low when reset is asserted.
This pin may be pulled up to V
DD
with a resistor consistent with the sink and leakage
current specifications of the output. Behavior is otherwise identical to the RST pin.
Watchdog Output. WDO is an active-low, push-pull output that goes low if the
microprocessor does not toggle WDI within 1.6s and WDI is not tri-stated. WDO is
usually connected to the non-maskable interrupt input of a microprocessor. When V
DD
drops below the reset threshold, WDO will go low whether or not the watchdog timer
has timed out. Reset is simultaneously asserted, thus preventing an interrupt. Since
floating WDI disables the internal timer, WDO goes low only when V
DD
drops below the
reset threshold, thus functioning as a low line output.
3
4
3
4
3
4
GND
PFI
5
6
5
6
5
6
PFO
WDI
7
-
-
RST
-
-
7
-
-
7
RST
RST_OD
8
8
8
WDO
2
FN8262.0
March 30, 2012
INTERSIL [ INTERSIL CORPORATION ]
