82C237
Timing Waveforms (Continued)
S0
S11
S12
S13
S14
S21
S22
S23
S24
S11/SI
CLK
TCLSH
(33)
(34)
TCLSL
(33)
TCLSH
(34)
TCLSL
(33)
TCLSH
TWHSH
(60)
ADSTB
A0-A7
(7)
TAHS
(59) TRHSH
TAHS
(7)
TAFAB
(3)
TFAAB (22)
TASS (11)
ADDRESS VALID
ADDRESS VALID
TAFDB
(5)
(5) TAFDB
TASS
(11)
TFADB (24)
DB0-DB7
A8-A15
IN
A8-A15
OUT
(24)
TODH (28)
TDCL
(15)
(16) TDCTR
TAZRL
TFADB
TOVD
(29)
TAFAC
(4)
TIDH (26)
TFAC (23)
TIDS
(27)
(64)
MEMR
MEMW
TDCTW (17)
TDCL
(15)
TDCL
(15)
TAFAC
(4)
TFAC (23)
EXTENDED WRITE
TASS (11)
TAK
(9)
TAK(9)
TAHS
(7)
TASS (11)
TAHS
(7)
DWLE
(SEE NOTE)
TOEV (65)
EOP
TEPS (20)
(19) TEPH
TEPW
(21)
EXT EOP
FIGURE 13. MEMORY-TO-MEMORY TRANSFER
NOTE: For 16-bit mode, 82C237 only. In 8-bit mode this signal is always high impedance three-stated. Waveform shown is for a 16-bit memory-to-memory
transfer. For an 8-bit transfer in 16-bit mode, DWLE will go high at least TASS before the falling edge of ADSTB in S2, then low TAHS after the falling
edge of ADSTB, and will remain low until the next ADSTB where the cycle is repeated.
S2
S3
SW
SW
S4
CLK
(16)
TDCTR
(15)
TDCL
READ
(15)
TDCL
(17)
(15)TDCL
TDCTW
WRITE
READY
EXTENDED WRITE
(31)TRH
(32)TRS
(32) TRS
(31)
TRH
FIGURE 14. READY
NOTE: READY must not transition during the specified setup and hold times.
4-170
INTERSIL [ Intersil ]
