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5962-9054304MQA 参数 Datasheet PDF下载

5962-9054304MQA图片预览
型号: 5962-9054304MQA
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS高性能可编程DMA控制器 [CMOS High Performance Programmable DMA Controller]
分类和应用: 控制器
文件页数/大小: 25 页 / 161 K
品牌: INTERSIL [ Intersil ]
 浏览型号5962-9054304MQA的Datasheet PDF文件第16页浏览型号5962-9054304MQA的Datasheet PDF文件第17页浏览型号5962-9054304MQA的Datasheet PDF文件第18页浏览型号5962-9054304MQA的Datasheet PDF文件第19页浏览型号5962-9054304MQA的Datasheet PDF文件第21页浏览型号5962-9054304MQA的Datasheet PDF文件第22页浏览型号5962-9054304MQA的Datasheet PDF文件第23页浏览型号5962-9054304MQA的Datasheet PDF文件第24页  
82C237  
o
o
AC Electrical Specifications  
V
= +5.0V ±10%, GND = 0V, T = 0 C to +70 C (C82C237),  
CC A  
o
o
T = -40 C to +85 C (I82C237),  
T = -55 C to +125 C (M82C237) (Continued)  
A
o
o
A
82C237  
82C237-12  
SYMBOL  
PARAMETER  
MIN  
MAX  
MIN  
MAX  
UNITS  
ns  
(35)TWRRD  
(36)TRLRH  
(37)TSHSL  
(38)TWLWHA  
(39)TWLWH  
(40)TRLRHC  
(56)TAVRL  
(57)TAVWL  
(58)TRHAL  
(59)TRHSH  
(60)TWHSH  
(61)TDVRL  
(62)TDVWL  
(63)TRHDI  
(64)TAZRL  
(65)TOEV  
READ HIGH Delay from WRITE HIGH  
READ Pulse Width, Normal Timing  
ADSTB Pulse Width  
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
2TCY-55  
TCY-35  
2TCY-80  
TCY-80  
TCY-55  
17  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2TCY-60  
TCY-50  
2TCY-85  
TCY-85  
TCY-60  
17  
ns  
ns  
Extended WRITE Pulse Width  
WRITE Pulse Width  
ns  
ns  
READ Pulse Width, Compressed  
ADR Valid to READ LOW  
ns  
ns  
ADR Valid to WRITE LOW  
7
7
ns  
READ HIGH to AEN LOW  
15  
15  
ns  
READ HIGH to ADSTB HIGH  
WRITE HIGH to ADSTB HIGH  
DACK Valid to READ LOW  
13  
13  
ns  
15  
15  
ns  
25  
25  
ns  
DACK Valid to WRITE LOW  
READ HIGH to DACK Inactive  
ADR Float to READ LOW  
25  
25  
ns  
12  
12  
ns  
-2.5  
-2.5  
ns  
Output Enable Valid Before WRITE HIGH  
Output Enable Hold Time from WRITE HIGH  
TCY+20  
TCY-50  
TCY+20  
TCY-50  
ns  
(66)TOEH  
ns  
PERIPHERAL (SLAVE) MODE  
(41)TAR  
ADR Valid or CS LOW to READ LOW  
10  
0
-
0
0
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(42)TAWL  
(43)TCWL  
(44)TDW  
(45)TRA  
ADR Valid to WRITE LOW Setup Time  
CS LOW to WRITE LOW Setup Time  
Data Valid to WRITE HIGH Setup Time  
ADR or CS Hold from READ HIGH  
Data Access from READ  
-
0
-
0
-
100  
0
-
60  
0
-
-
-
(46)TRDE  
(47)TRDF  
(48)TRSTD  
(49)TRSTS  
(50)TRSTW  
(51)TRW  
(52)TWA  
-
120  
-
80  
55  
-
DB Float Delay from READ HIGH  
Power Supply HIGH to RESET LOW Setup Time  
RESET to First IOR or IOW  
5
85  
-
5
500  
2TCY  
300  
155  
0
500  
2TCY  
300  
85  
0
-
-
RESET Pulse Width  
-
-
READ Pulse Width  
-
-
ADR from WRITE HIGH Hold Time  
CS HIGH from WRITE HIGH Hold Time  
Data from WRITE HIGH Hold Time  
WRITE Pulse Width  
-
-
(53)TWC  
(54)TWD  
(55)TWWS  
0
-
0
-
10  
100  
-
10  
45  
-
-
-
4-167  
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