82C237
Figure 9 shows the data bus for a 16-bit DMA application The ADSTB inverted could be eliminated by using a 74F75
with the 82C237. High memory and low memory are falling edge D latch. The latch on D8-D15 is needed for 16-
selected accordingly with A0 and the 8/16 signal during DMA bit memory-to-memory transfers. The upper eight bits of
transfers. The 8/16 signal is formed from DWLE with a D flip- data are latched by MEMR during the read half of the trans-
flop and ADSTB. ADSTB must be inverted to the D flip-flop fer. The data is then enabled onto the data bus during the
since DWLE is set up to the falling edge of ADSTB and the write half of the transfer.
74F74 latches data on the rising edge of CLK.
80C286
TRANSCEIVER
TRANSCEIVER
HIGH
D8-D15
D0 - D7
D8-D15
MEMORY
CS
D0-D7
LATCH
(SEE NOTE)
LOW
MEMORY
82C237
OE
CS
D0-D7
STB
V
CC
IOR
IOW
I/O
DEVICE
MEMR
MEMW
74F74
DWLE
8/16
I/O
D
Q
DEVICE
ADSTB
A0
CLK
HLDA
MEMCS
FROM DECODER
NOTE: Only needed for memory-to-memory transfers.
FIGURE 9. DATA BUS FOR 16-BIT DMA APPLICATION
4-164
INTERSIL [ Intersil ]
