82C237
o
o
AC Electrical Specifications
V
= +5.0V ±10%, GND = 0V, T = 0 C to +70 C (C82C237),
CC A
o
o
T = -40 C to +85 C (I82C237),
T = -55 C to +125 C (M82C237)
A
o
o
A
82C237
82C237-12
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
UNITS
DMA (MASTER) MODE
(1)TAEL
(2)TAET
(3)TAFAB
(4)TAFC
(5)TAFDB
(6)TAHR
(7)TAHS
(8)TAHW
(9)TAK
AEN HIGH from CLK LOW (S1) Delay Time
AEN LOW from CLK HIGH (SI) Delay Time
ADR Active to Float Delay from CLK HIGH
READ or WRITE Float Delay from CLK HIGH
DB Active to Float Delay from CLK HIGH
ADR from READ HIGH Hold Time
DB from ADSTB LOW Hold Time
-
-
-
-
-
105
80
55
75
135
-
-
50
50
55
50
90
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
TCY-75
TCY-65
TCL-18
-
TCL-18
-
ADR from WRITE HIGH Hold Time
DACK Valid from CLK LOW Delay Time
EOP HIGH from CLK HIGH Delay Time
EOP LOW from CLK HIGH Delay Time
ADR Stable from CLK HIGH
TCY-65
-
TCY-50
-
-
105
105
60
60
-
-
69
90
35
50
-
-
-
-
-
(10)TASM
(11)TASS
(12)TCH
-
-
DB to ADSTB LOW Setup Time
TCH-20
TCH-20
CLK HIGH Time (Transitions 10ns)
CLK LOW Time (Transitions 10ns)
CLK Cycle Time
55
-
30
-
(13)TCL
43
-
30
-
(14)TCY
125
-
80
-
(15)TDCL
(16)TDCTR
(17)TDCTW
(18)TDQ
CLK HIGH to READ or WRITE LOW Delay
READ HIGH from CLK HIGH (S4) Delay Time
WRITE HIGH from CLK HIGH (S4) Delay Time
HRQ Valid from CLK HIGH Delay Time
EOP Hold Time from CLK LOW (S2)
EOP LOW to CLK LOW Setup Time
EOP Pulse Width
-
130
115
80
75
-
-
120
80
70
30
-
-
-
-
-
-
-
(19)TEPH
(20)TEPS
(21)TEPW
(22)TFAAB
(23)TFAC
(24)TFADB
(25)THS
90
50
25
-
0
-
135
-
50
-
ADR Valid Delay from CLK HIGH
-
60
90
60
-
-
50
50
45
-
READ or WRITE Active from CLK HIGH
DB Valid Delay from CLK HIGH
-
-
-
-
HLDA Valid to CLK HIGH Setup Time
Input Data from MEMR HIGH Hold Time
Input Data to MEMR HIGH Setup Time
Output Data from MEMW HIGH Hold Time
Output Data Valid to MEMW HIGH
DREQ to CLK LOW (SI, S4) Setup Time
CLK to READY LOW Hold Time
45
10
(26)TIDH
(27)TIDS
(28)TODH
(29)TODV
(30)TQS
0
-
0
-
90
-
45
-
15
-
TCY-50
-
TCY-35
-
TCY-10
-
0
20
35
-
-
0
10
15
-
-
(31)TRH
-
-
(32)TRS
READY to CLK LOW Setup Time
-
-
(33)TCLSH
(34)TCLSL
ADSTB HIGH from CLK LOW Delay Time
ADSTB LOW from CLK LOW Delay Time
70
120
70
60
-
-
4-166
INTERSIL [ Intersil ]
