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TE28F128J3C-150 参数 Datasheet PDF下载

TE28F128J3C-150图片预览
型号: TE28F128J3C-150
PDF下载: 下载PDF文件 查看货源
内容描述: 英特尔StrataFlash闪存( J3 ) [Intel StrataFlash Memory (J3)]
分类和应用: 闪存
文件页数/大小: 72 页 / 909 K
品牌: INTEL [ INTEL ]
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256-Mbit J3 (x8/x16)  
suspended (and programming is inactive), program is suspended, or the device is in reset/power-  
down mode. Additionally, the configuration command allows the STS signal to be configured to  
pulse on completion of programming and/or block erases.  
Three CE signals are used to enable and disable the device. A unique CE logic design (see  
Table 13, “Chip Enable Truth Table” on page 33) reduces decoder logic typically required for  
multi-chip designs. External logic is not required when designing a single chip, a dual chip, or a 4-  
chip miniature card or SIMM module.  
The BYTE# signal allows either x8 or x16 read/writes to the device. BYTE#-low selects 8-bit  
mode; address A0 selects between the low byte and high byte. BYTE#-high enables 16-bit  
operation; address A1 becomes the lowest order address and address A0 is not used (don’t care). A  
device block diagram is shown in Figure 4 on page 14.  
When the device is disabled (see Table 13 on page 33), with CEx at VIH and RP# at VIH, the  
standby mode is enabled. When RP# is at VIL, a further power-down mode is enabled which  
minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is  
required from RP# going high until data outputs are valid. Likewise, the device has a wake time  
(tPHWL) from RP#-high until writes to the CUI are recognized. With RP# at VIL, the WSM is reset  
and the Status Register is cleared.  
2.1  
Block Diagram  
Figure 1. 3 Volt Intel StrataFlash® Memory Block Diagram  
D[15:0]  
Output  
Buffer  
VCCQ  
Input Buffer  
VCC  
Query  
I/O Logic  
BYTE#  
CE0  
CE1  
CE2  
WE#  
OE#  
RP#  
Identifier  
Register  
CE  
Logic  
Command  
User  
Interface  
Status  
Register  
Multiplexer  
A[2:0]  
Data  
Comparator  
Y-Decoder  
Y-Gating  
STS  
Input Buffer  
A[MAX:MIN]  
Write State  
Machine  
VPEN  
Program/Erase  
Voltage Switch  
32-Mbit: Thirty-two  
64-Mbit: Sixty-four  
128-Mbit: One-hundred  
twenty-eight  
Address  
Latch  
VCC  
GND  
X-Decoder  
128-Kbyte Blocks  
Address  
Counter  
Datasheet  
9