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TE28F128J3C-150 参数 Datasheet PDF下载

TE28F128J3C-150图片预览
型号: TE28F128J3C-150
PDF下载: 下载PDF文件 查看货源
内容描述: 英特尔StrataFlash闪存( J3 ) [Intel StrataFlash Memory (J3)]
分类和应用: 闪存
文件页数/大小: 72 页 / 909 K
品牌: INTEL [ INTEL ]
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Contents  
Revision History  
Date of  
Version  
Revision  
Description  
07/07/99  
08/03/99  
-001  
-002  
Original Version  
A –A indicated on block diagram  
0
2
Changed Minimum Block Erase time,I , I , Page Mode and Byte Mode  
currents. Modified RP# on AC Waveform for Write Operations  
OL OH  
09/07/99  
12/16/99  
-003  
-004  
Changed Block Erase time and t  
AVWH  
Removed all references to 5 V I/O operation  
Corrected Ordering Information, Valid Combinations entries  
Changed Min program time to 211 µs  
Added DU to Lead Descriptions table  
Changed Chip Scale Package to Ball Grid Array Package  
Changed default read mode to page mode  
Removed erase queuing from Figure 10, Block Erase Flowchart  
Added Program Max time  
Added Erase Max time  
Added Max page mode read current  
Moved tables to correspond with sections  
Fixed typographical errors in ordering information and DC parameter table  
Removed V  
setting and changed V  
to V  
CCQ1  
CCQ2/3 CCQ1/2  
03/16/00  
-005  
Added recommended resister value for STS pin  
Change operation temperature range  
Removed note that rp# could go to 14 V  
Removed V of 0.45 V; Removed V of 2.4 V  
OL  
OH  
Updated I  
Typ values  
CCR  
Added Max lock-bit program and lock times  
Added note on max measurements  
Updated cover sheet statement of 700 million units to one billion  
Corrected Table 10 to show correct maximum program times  
Corrected error in Max block program time in section 6.7  
Corrected typical erase time in section 6.7  
06/26/00  
-006  
Updated cover page to reflect 100K minimum erase cycles  
Updated cover page to reflect 110 ns 32M read speed  
Removed Set Read Configuration command from Table 4  
Updated Table 8 to reflect reserved bits are 1-7; not 2-7  
Updated Table 16 bit 2 definition from R to PSS  
Changed V  
Max voltage from 0.8 V to 2.0 V, Section 6.4, DC  
PENLK  
Characteristics  
2/15/01  
-007  
Updated 32Mbit Read Parameters R1, R2 and R3 to reflect 110ns, Section 6.5,  
AC Characteristics–Read-Only Operations (1,2)  
Updated write parameter W13 (t  
) from 90 ns to 500 ns, Section 6.6, AC  
WHRL  
Characteristics–Write Operations  
Updated Max. Program Suspend Latency W16 (t  
) from 30 to 75 µs,  
WHRH1  
Section 6.7, Block Erase, Program, and Lock-Bit Configuration Performance  
(1,2,3)  
04/13/01  
-008  
Revised Section 7.0, Ordering Information  
Datasheet  
5