Contents
Date of
Revision
Version
Description
Added Figure 4, 3 Volt Intel StrataFlash® Memory VF BGA Package (32 Mbit)
Added Figure 5, 3 Volt Intel StrataFlash® Memory VF BGA Mechanical
Specifications
Updated Operating Temperature Range to Extended (Section 6.1 and Table 22)
Reduced t
to 35 ns. Reduced t
to 0 ns
WHEH
07/27/01
-009
EHQZ
Added parameter values for –40 °C operation to Lock-Bit and Suspend Latency
Updated V and V to 2.2 V
LKO
PENLK
Removed Note #4, Section 6.4 and Section 6.6
Minor text edits
Added notes under lead descriptions for VF BGA Package
Removed 3.0 V - 3.6 V Vcc, and Vccq columns under AC Characteristics
Removed byte mode read current row un DC characteristics
Added ordering information for VF BGA Package
Minor text edits
10/31/01
03/21/02
-010
-011
Changed datasheet to reflect the best known methods
Updated max value for Clear Block Lock-Bits time
Minor text edits
12/12/02
01/24/03
-012
-013
Added nomenclature for J3C (0.18 µm) devices.
Added 115 ns access speed 64 Mb J3C device. Added 120 ns access speed 128
Mb J3C device. Added “TE” package designator for J3C TSOP package.
Revised Asynchronous Page Read description. Revised Write-to-Buffer flow
chart. Updated timing waveforms. Added 256-Mbit J3C pinout.
12/09/03
1/3/04
-014
-015
Added 256Mbit device timings, device ID, and CFI information. Also corrected
VLKO specification.
1/23/04
1/23/04
5/19/04
7/7/04
-016
-016
-018
-019
Corrected memory block count from 257 to 255.
Memory block count fix.
Restructured the datasheet layout.
Added lead-free part numbers and 8-word page information.
Added Note to DC Voltage Characteristics table; “Speed Bin” to Read Operations
table; Corrected format for AC Waveform for Reset Operation figure; Corrected
“R” and “8W” headings in Enhanced Configuration Register table because they
were transposed; Added 802 and 803 to ordering information and corrected 56-
Lead TSOP combination number.
11/23/04
3/24/05
-020
-021
Corrected ordering information.
6
Datasheet
INTEL [ INTEL ]
