256-Mbit J3 (x8/x16)
3.3
VF-BGA (J3) Package
Figure 5. Intel StrataFlash® Memory (J3) VF BGA Mechanical Specifications
B a ll A 1
C o r n e r
B all A1
C o rn e r
D
S 1
S 2
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
E
e
b
T o p V ie w
A 1
-
B u m p S id e D o w n
B o tt o m V ie w
-
B a ll S id e U p
A 2
A
S e a t in g
P la n e
Y
S id e V ie w
N
o te :
D
r a w in g n o t t o s ca le
D im e n s io n s T a b le
M illim e te rs
I n c h e s
S y m b o l
A
M
in
N o m
M
a x
N o te s
M
in
N o m
M a x
Pa c k a g e H e ig h t
1 . 0 0 0
0 . 0 3 9 4
1
Ba ll H e ig h t
A
A
0 . 1 5 0
0 . 0 0 5 9
2
Pa c k a g e B o d y T h ic k n e s s
0 .6 6 5
0 .3 7 5
7 .2 8 6
1 0 . 8 5 0
0 .7 5 0
4 8
0 .0 2 6 2
0 .0 1 4 8
0 .2 8 6 8
0 .4 2 7 2
0 .0 2 9 5
4 8
Ba ll (L e a d )
W
id th
b
D
E
0 . 3 2 5
7 . 1 8 6
0 . 4 2 5
7 . 3 8 6
0 . 0 1 2 8
0 . 2 8 2 9
0 . 4 2 3 2
0 . 0 1 6 7
0 . 2 9 0 8
0 . 4 3 1 1
1
1
Pa c k a g e B o d y L e n g t h
Pitc h
Ba ll (L e a d ) C o u n t
1 0 .7 5 0
1 0 .9 5 0
[ e ]
N
Se a tin g P la n e C o p la n a r ity
Co r n e r to B a ll A 1 D is ta n c e
Co r n e r to B a ll A 1 D is ta n c e
Y
0 . 1 0 0
1 . 1 1 8
3 . 6 5 0
0 . 0 0 3 9
0 . 0 4 4 0
0 . 1 4 3 7
1
A
A
lo n g
lo n g
D
E
S
0 . 9 1 8
3 . 4 5 0
1 .0 1 8
3 .5 5 0
1
1
0 . 0 3 6 1
0 . 1 3 5 8
0 .0 4 0 1
0 .1 3 9 8
2
S
N o te : ( 1 ) P a c k a g e d im e n s io n s a re f o r r e f e re n c e o n ly . T h e s e d im e n s io n s a re e s t im a te s b a s e d o n d ie s iz e ,
a n d a r e s u b j e c t t o c h a n g e .
NOTES:
1. For Daisy Chain Evaluation Unit information refer to the Intel Flash Memory Packaging Technology Web
page at; www.intel.com/design/packtech/index.htm
2. For Packaging Shipping Media information refer to the Intel Flash Memory Packaging Technology Web page
at; www.intel.com/design/packtech/index.htm
Datasheet
13
INTEL [ INTEL ]
