256-Mbit J3 (x8/x16)
Table 31. Protection Register Information
Offset(1)
P = 31h
Description
(Optional Flash Features and Commands)
Hex
Code
Length
Add.
Value
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection bytes are available
(P+E)h
1
4
3F:
--01
01
Protection Field 1: Protection Description
This field describes user-available One Time Programmable
(OTP) Protection Register bytes. Some are pre-programmed
with device-unique serial numbers. Others are user-
programmable. Bits 0-15 point to the Protection Register lock
byte, the section’s first byte. The following bytes are factory
pre-programmed and user-programmable.
40:
41:
42:
43:
--80
--00
--03
--03
80h
00h
(P+F)h
(P+10)h
(P+11)h
(P+12)h
8bytes
8bytes
bits 0-7 = Lock/bytes JEDEC-plane physical low address
bits 8-15 = Lock/bytes JEDEC-plane physical high address
bits 16-23 = “n” such that 2n = factory pre-programmed bytes
bits 24-31 = “n” such that 2n = user-programmable bytes
NOTE:
1. The variable P is a pointer which is defined at CFI offset 15h.
Table 32. Burst Read Information
Offset(1)
P = 31h
Description
(Optional Flash Features and Commands)
Hex
Code
Length
Add.
Value
Page Mode Read capability
bits 0–7 = “n” such that 2n HEX value represents the number
of read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h indicates no
read page buffer.
(P+13)h
1
1
44:
--03
--00
8 byte
0
Number of synchronous mode read configuration fields that
follow. 00h indicates no burst capability.
(P+14)h
45:
46:
(P+15)h
Reserved for future use
NOTE:
1. The variable P is a pointer which is defined at CFI offset 15h.
58
Datasheet
INTEL [ INTEL ]
