256-Mbit J3 (x8/x16)
Table 27. CFI Identification (Sheet 2 of 2)
Hex
Code
Offset Length
Description
Add.
Value
0000h means no second vendor-specified algorithm exists
Secondary algorithm Extended Query Table address.
0000h means none exists
18:
19:
1A:
--00
--00
--00
19h
2
A.5
System Interface Information
The following device information can optimize system interface software.
Table 28. System Interface Information
Hex
Code
Offset Length
Description
Add.
Value
V
V
V
V
logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
CC
1Bh
1Ch
1Dh
1Eh
1
1
1
1
1B:
--27
--36
--00
--00
2.7 V
logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
CC
1C:
1D:
1E:
3.6 V
0.0 V
0.0 V
[programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
PP
[programming] supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
PP
1Fh
20h
21h
22h
1
1
1
1
“n” such that typical single word program time-out = 2n µs
“n” such that typical max. buffer write time-out = 2n µs
“n” such that typical block erase time-out = 2n ms
“n” such that typical full chip erase time-out = 2n ms
“n” such that maximum word program time-out = 2n times
typical
1F:
20:
21:
22:
--08
--08
--0A
--00
256 µs
256 µs
1 s
NA
23h
1
23:
--04
2 ms
24h
25h
26h
1
1
1
“n” such that maximum buffer write time-out = 2n times typical
“n” such that maximum block erase time-out = 2n times typical
“n” such that maximum chip erase time-out = 2n times typical
24:
25:
26:
--04
--04
--00
2 ms
16 s
NA
A.6
Device Geometry Definition
This field provides critical details of the flash device geometry.
Table 29. Device Geometry Definition (Sheet 1 of 2)
Code See Table
Below
Offset Length
Description
27h
28h
1
2
“n” such that device size = 2n in number of bytes
27:
x8/
x16
Flash device interface: x8 async x16 async x8/x16 async
28:
--02
28:00,29:00 28:01,29:00 28:02,29:00
“n” such that maximum number of bytes in write buffer = 2n
29:
2A:
2B:
--00
--05
--00
2Ah
2
32
Datasheet
55
INTEL [ INTEL ]
