256-Mbit J3 (x8/x16)
Table 21. Byte-Wide Protection Register Addressing (Sheet 2 of 2)
6
7
Factory
Factory
User
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
8
9
User
A
B
C
D
E
F
User
User
User
User
User
User
NOTE: All address lines not specified in the above table must be 0 when accessing the Protection Register,
i.e.g., A[MAX:9] = 0.
13.4
Array Protection
The VPEN signal is a hardware mechanism to prohibit array alteration. When the VPEN voltage is
below the VPENLK voltage, array contents cannot be altered. To ensure a proper erase or program
operation, VPEN must be set to a valid voltage level. To determine the status of an erase or program
operation, poll the Status Register and analyze the bits.
Datasheet
49
INTEL [ INTEL ]
