256-Mbit J3 (x8/x16)
Figure 17. Protection Register Memory Map
A[24:1]: 256 Mbit A[22:1]: 64 Mbit
Word
Address
A[23:1]: 128 Mbit A[21:1]: 32 Mbit
0x88
64-bit Segment
(User-Programmable)
0x85
0x84
128-Bit Protection Register 0
64-bit Segment
(Factory-Programmed)
0x81
0x80
Lock Register 0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
NOTE: A0 is not used in x16 mode when accessing the Protection Register map (See Table 8 for x16
addressing). For x8 mode A0 is used (See Table 21 for x8 addressing).
Table 20. Word-Wide Protection Register Addressing
Word
Use
A8
A7
A6
A5
A4
A3
A2
A1
LOCK
Both
Factory
Factory
Factory
Factory
User
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
2
3
4
5
6
7
User
User
User
Table 21. Byte-Wide Protection Register Addressing (Sheet 1 of 2)
Byte
Use
A8
A7
A6
A5
A4
A3
A2
A1
A0
LOCK
Both
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
LOCK
Both
0
1
2
3
4
5
Factory
Factory
Factory
Factory
Factory
Factory
48
Datasheet
INTEL [ INTEL ]
