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TE28F008S5-100 参数 Datasheet PDF下载

TE28F008S5-100图片预览
型号: TE28F008S5-100
PDF下载: 下载PDF文件 查看货源
内容描述: 字节宽的SMART 5 FlashFile Memory系列4 ,8和16 MBIT [BYTE-WIDE SMART 5 FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 37 页 / 505 K
品牌: INTEL [ INTEL ]
 浏览型号TE28F008S5-100的Datasheet PDF文件第7页浏览型号TE28F008S5-100的Datasheet PDF文件第8页浏览型号TE28F008S5-100的Datasheet PDF文件第9页浏览型号TE28F008S5-100的Datasheet PDF文件第10页浏览型号TE28F008S5-100的Datasheet PDF文件第12页浏览型号TE28F008S5-100的Datasheet PDF文件第13页浏览型号TE28F008S5-100的Datasheet PDF文件第14页浏览型号TE28F008S5-100的Datasheet PDF文件第15页  
E
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY  
3.5  
Read Identifier Codes  
Operation  
1FFFFF  
Block 31  
Reserved for  
The read identifier codes operation outputs the  
manufacturer code, device code, block lock  
configuration codes for each block, and master lock  
configuration code (see Figure 5). Using the  
manufacturer and device codes, the system  
software can automatically match the device with its  
proper algorithms. The block lock and master lock  
configuration codes identify locked and unlocked  
blocks and master lock-bit setting.  
Future Implementation  
1F0002  
Block 31 Lock Configuration  
Reserved for  
1F0000  
Future Implementation  
(Blocks 16 through 30)  
0FFFFF  
Block 15  
Reserved for  
Future Implementation  
3.6  
Write  
0F0002  
0F0000  
Block 15 Lock Configuration  
The CUI does not occupy an addressable memory  
location. It is written when WE# and CE# are active  
and OE# = VIH. The address and data needed to  
execute a command are latched on the rising edge  
of WE# or CE# (whichever goes high first).  
Standard microprocessor write timings are used.  
Figure 17 illustrates a write operation.  
Reserved for  
Future Implementation  
(Blocks 8 through 14)  
07FFFF  
16-Mbit  
Block 7  
Reserved for  
Future Implementation  
070002  
070000  
Block 7 Lock Configuration  
4.0 COMMAND DEFINITIONS  
Reserved for  
Future Implementation  
When the VPP voltage VPPLK, read operations  
from the status register, identifier codes, or blocks  
are enabled. Placing VPPH1/2 on VPP enables  
successful block erase, program, and lock-bit  
configuration operations.  
8-Mbit  
(Blocks 2 through 14)  
01FFFF  
Block 1  
Reserved for  
Future Implementation  
4-Mbit  
Device operations are selected by writing specific  
commands into the CUI. Table 3 defines these  
commands.  
010002  
Block 1 Lock Configuration  
Reserved for  
010000  
00FFFF  
Future Implementation  
Block 0  
Reserved For  
Future Implementation  
000003  
000002  
000001  
000000  
Master Lock Configuration  
Block 0 Lock Configuration  
Device Code  
Manufacturer Code  
Figure 5. Device Identifier Code Memory Map  
11  
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