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TE28F008S5-100 参数 Datasheet PDF下载

TE28F008S5-100图片预览
型号: TE28F008S5-100
PDF下载: 下载PDF文件 查看货源
内容描述: 字节宽的SMART 5 FlashFile Memory系列4 ,8和16 MBIT [BYTE-WIDE SMART 5 FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 37 页 / 505 K
品牌: INTEL [ INTEL ]
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E
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY  
Table 1. Pin Descriptions  
Name and Function  
Sym  
Type  
A0–A20  
INPUT ADDRESS INPUTS: Inputs for addresses during read and write operations.  
Addresses are internally latched during a write cycle.  
4 Mbit A0–A18  
8 Mbit A0–A19  
16 Mbit A0–A20  
DQ0–DQ7 INPUT/ DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles;  
OUTPUT outputs data during memory array, status register, and identifier code read cycles.  
Data pins float to high-impedance when the chip is deselected or outputs are  
disabled. Data is internally latched during a write cycle.  
CE#  
INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and  
sense amplifiers. CE#-high deselects the device and reduces power consumption to  
standby levels.  
RP#  
INPUT RESET/DEEP POWER-DOWN: When driven low, RP# inhibits write operations  
which provides data protection during power transitions, puts the device in deep  
power-down mode, and resets internal automation. RP#-high enables normal  
operation. Exit from deep power-down sets the device to read array mode.  
RP# at VHH enables setting of the master lock-bit and enables configuration of block  
lock-bits when the master lock-bit is set. RP# = VHH overrides block lock-bits,  
thereby enabling block erase and program operations to locked memory blocks.  
Block erase, program, or lock-bit configuration with VIH < RP# < VHH produce  
spurious results and should not be attempted.  
OE#  
WE#  
INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.  
INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data  
are latched on the rising edge of the WE# pulse.  
RY/BY#  
OUTPUT READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is  
performing an internal operation (block erase, program, or lock-bit configuration).  
RY/BY#-high indicates that the WSM is ready for new commands, block erase or  
program is suspended, or the device is in deep power-down mode. RY/BY# is  
always active.  
VPP  
SUPPLY BLOCK ERASE, PROGRAM, LOCK-BIT CONFIGURATION POWER SUPPLY:  
For erasing array blocks, programming data, or configuring lock-bits.  
Smart 5 Flash 5V and 12V VPP  
With VPP VPPLK, memory contents cannot be altered. Block erase, program, and  
lock-bit configuration with an invalid VPP (see DC Characteristics) produce spurious  
results and should not be attempted.  
VCC  
SUPPLY DEVICE POWER SUPPLY: Internal detection automatically configures the device  
for optimized read performance. Do not float any power pins.  
Smart 5 Flash 5V VCC  
With VCC VLKO, all write attempts to the flash memory are inhibited. Device  
operations at invalid VCC voltages (see DC Characteristics) produce spurious  
results and should not be attempted.  
GND  
NC  
SUPPLY GROUND: Do not float any ground pins.  
NO CONNECT: Lead is not internally connected; it may be driven or floated.  
7
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