E
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
Table 3. Command Definitions(9)
Bus Cycles First Bus Cycle
Notes Oper(1) Addr(2) Data(3) Oper(1) Addr(2) Data(3)
Second Bus Cycle
Command
Req’d.
Read Array/Reset
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
1
≥ 2
2
Write
Write
Write
Write
Write
Write
X
X
FFH
90H
70H
50H
20H
4
Read
Read
IA
X
ID
X
SRD
1
X
2
5
BA
PA
Write
Write
BA
PA
D0H
PD
Program
2
5,6
40H
or
10H
Block Erase and Program
Suspend
1
1
5
5
Write
Write
X
X
B0H
Block Erase and Program
Resume
D0H
Set Block Lock-Bit
Set Master Lock-Bit
Clear Block Lock-Bits
NOTES:
2
2
2
7
7
8
Write
Write
Write
BA
X
60H
60H
60H
Write
Write
Write
BA
X
01H
F1H
D0H
X
X
1. Bus operations are defined in Table 2.
2. X = Any valid address within the device.
IA = Identifier Code Address: see Figure 5.
BA = Address within the block being erased or locked.
PA = Address of memory location to be programmed.
3. SRD = Data read from status register. See Table 6 for a description of the status register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
ID = Data read from identifier codes.
4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock
codes. See Section 4.2 for read identifier code data.
5. If the block is locked, RP# must be at VHH to enable block erase or program operations. Attempts to issue a block erase or
program to a locked block while RP# is VIH will fail.
6. Either 40H or 10H are recognized by the WSM as the program setup.
7. If the master lock-bit is set, RP# must be at VHH to set a block lock-bit. RP# must be at VHH to set the master lock-bit. If the
master lock-bit is not set, a block lock-bit can be set while RP# is V .
IH
8. If the master lock-bit is set, RP# must be at VHH to clear block lock-bits. The clear block lock-bits operation simultaneously
clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is V .
IH
9. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
13
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