E
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
Start
Bus
Operation
Command
Comments
Data = 60H
Addr = X
Clear Block
Lock-Bits Setup
Write
Write 60H
Data = D0H
Addr = X
Clear Block
Lock-Bits Confirm
Write
Read
Write D0H
Status Register Data
Read Status
Register
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
0
SR.7 =
1
Write FFH after the Clear Block Lock-Bits operation to place device
to read array mode.
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Read Status Register
Data (See Above)
Command
Comments
Check SR.3
Standby
1 = V Error Detect
PP
1
SR.3 =
0
V
Range Error
PP
Check SR.1
1 = Device Protect Detect
Standby
RP# = V , Master Lock-Bit Is Set
IH
1
1
Check SR.4,5
Both 1 = Command Sequence Error
Device Protect Error
SR.1=
0
Standby
Standby
Check SR.5
1 = Clear Block Lock-Bits Error
Command Sequence
Error
SR.4,5 =
0
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
1
Clear Block Lock-Bits
Error
SR.5 =
0
Clear Block Lock-Bits
Successful
Figure 12. Clear Block Lock-Bits Flowchart
27
PRELIMINARY
INTEL [ INTEL ]
