BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
E
Start
Bus
Command
Comments
Operation
Set
Data = 60H
Addr = Block Address (Block),
Device Address (Master)
Write
Write
Write 60H,
Block/Device Address
Block/Master
Lock-Bit Setup
Set
Data = 01H (Block),
F1H (Master)
Write 01H/F1H,
Block/Device Address
Block or Master
Lock-Bit Confirm Addr = Block Address (Block),
Device Address (Master)
Read
Status Register Data
Read Status
Register
Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby
0
SR.7 =
Repeat for subsequent lock-bit set operations.
Full status check can be done after each lock-bit set operation or after
a sequence of lock-bit set operations.
1
Write FFH after the last lock-bit set operation to place device in
read array mode.
Full Status
Check if Desired
Set Lock-Bit Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Read Status Register
Data (See Above)
Command
Comments
Check SR.3
Standby
1 = V Error Detect
PP
1
SR.3 =
0
V
Range Error
PP
Check SR.1
1 = Device Protect Detect
Standby
RP# = V
,
IH
(Set Master Lock-Bit Operation)
RP# = V , Master Lock-Bit Is Set
(Set Block Lock-Bit Operation)
HH
1
1
Device Protect Error
SR.1 =
0
Standby
Standby
Check SR.4,5
Both 1 = Command Sequence Error
Check SR.4
1 = Set Lock-Bit Reset Error
Command Sequence
Error
SR.4,5 =
0
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple lock-bits are set before
full status is checked.
If error is detected, clear the Status Register before attempting retry
or other error recovery.
1
Set Lock-Bit Error
SR.4 =
0
Set Lock-Bit Successful
Figure 11. Set Block and Master Lock-Bit Flowchart
26
PRELIMINARY
INTEL [ INTEL ]
