28F640L30, 28F128L30, 28F256L30
2.4
Signal Descriptions for VF BGA Package
Table 1 describes the active signals used on the L30 flash memory device.
Table 1. Signal Descriptions
Symbol
Type
In
Name and Function
A[MAX:0]
ADDRESS: Device address inputs. 64-Mbit: A[21:0]; 128-Mbit: A[22:0]; 256-Mbit: A[23:0].
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during memory,
Status Register, Protection Register, and Read Configuration Register reads. Data balls float when the
CE# or OE# are de-asserted. Data is internally latched during writes.
D[15:0]
In/Out
ADDRESS VALID: Active-low input. During synchronous read operations, addresses are latched on
the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
ADV#
CE#
In
In
In
In asynchronous mode, the address is latched when ADV# going high or continuously flows through if
ADV# is held low.
CHIP ENABLE: Active-low input. CE#-low selects the device. CE#-high deselects the device, placing it
in standby, with D[15:0] and WAIT in High-Z.
CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode and
increments the internal address generator. During synchronous read operations, addresses are
latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs
first.
CLK
OUTPUT ENABLE: Active-low input. OE#-low enables the device’s output data buffers during read
cycles. OE#-high places the data outputs in High-Z and WAIT in High-Z.
OE#
In
In
RESET: Active-low input. RST# resets internal automation and inhibits write operations. This provides
data protection during power transitions. RST#-high enables normal operation. Exit from reset places
the device in asynchronous read array mode.
RST#
WAIT: Indicates data valid in synchronous array or non-array burst reads. Configuration Register bit 10
(CR.10, WT) determines its polarity when asserted. With CE# and OE# at V , WAIT’s active output is
IL
V
or V when CE# and OE# are asserted. WAIT is high-Z if CE# or OE# is V .
OL
O
H
I
H
WAIT
Out
•
In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
valid data when de-asserted.
•
In asynchronous page mode, and all write modes, WAIT is de-asserted.
WRITE ENABLE: Active-low input. WE# controls writes to the device. Address and data are latched on
the rising edge of WE#.
WE#
WP#
In
In
WRITE PROTECT: Active-low input. WP#-low enables the lock-down mechanism. Blocks in lock-down
cannot be unlocked with the Unlock command. WP#-high overrides the lock-down function enabling
blocks to be erased or programmed using software commands.
ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming. Memory
contents cannot be altered when V ≤ V
. Block erase and program at invalid V voltages should
PP
PPLK
PP
not be attempted.
Set V = V for in-system program and erase operations. To accommodate resistor or diode drops
PP
CC
VPP
VCC
Pwr/l
Pwr
from the system supply, the V level of V can be as low as V
min to perform in-system flash modification. VPP may be 0 V during read operations.
min. V must remain above V
IH
PP
PP1 PP PP1
V
can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles.
VPP can be connected to 12 V for a cumulative total not to exceed 80 hours. Extended use of this pin
at 12 V may reduce block cycling capability.
PP2
DEVICE CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited
when V ≤ V
. Operations at invalid V voltages should not be attempted.
CC
LKO
CC
VCCQ
VSS
Pwr
Pwr
Pwr
OUTPUT POWER SUPPLY: Output-driver source voltage.
GROUND: Ground reference for device logic voltages. Connect to system ground.
GROUND: Ground reference for device output voltages. Connect to system ground.
VSSQ
DON’T USE: Do not use this ball. This ball should not be connected to any power supplies, signals or
other balls, and must be left floating.
DU
-
NC
-
-
NO CONNECT: No internal connection; can be driven or floated.
RFU
RESERVED for FUTURE USE: Reserved by Intel for future device functionality and enhancement.
12
Datasheet
INTEL [ INTEL ]
