LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII
Table 1. LXT9763 MII Signal Descriptions (Continued)
Pin#
Symbol
Type1
Signal Description2
51
50
49
48
RXD1_0
Receive Data - Port 1. Data received at network port 1 is output in 4-bit parallel
nibbles, driven synchronously to RX_CLK. In symbol mode (16.11 = 1), the receive
error signals are re-mapped to provide a fifth data bit.
RXD1_1
RXD1_2
RXD1_3
O
35
34
33
30
RXD2_0
RXD2_1
RXD2_2
RXD2_3
Receive Data - Port 2. Data received at network port 2 is output in 4-bit parallel
nibbles, driven synchronously to RX_CLK. In symbol mode (16.11 = 1), the receive
error signals are re-mapped to provide a fifth data bit.
O
O
O
O
17
14
13
12
RXD3_0
RXD3_1
RXD3_2
RXD3_3
Receive Data - Port 3. Data received at network port 3 is output in 4-bit parallel
nibbles, driven synchronously to RX_CLK. In symbol mode (16.11 = 1), the
receive error signals are re-mapped to provide a fifth data bit.
205
204
203
202
RXD4_0
RXD4_1
RXD4_2
RXD4_3
Receive Data - Port 4. Data received at network port 4 is output in 4-bit parallel
nibbles, driven synchronously to RX_CLK. In symbol mode (16.11 = 1), the
receive error signals are re-mapped to provide a fifth data bit.
187
186
185
184
RXD5_0
RXD5_1
RXD5_2
RXD5_3
Receive Data - Port 5. Data received at network port 5 is output in 4-bit parallel
nibbles, driven synchronously to RX_CLK. In symbol mode (16.11 = 1), the
receive error signals are re-mapped to provide a fifth data bit.
86
65
47
29
11
CRS0
CRS1
CRS2
CRS3
CRS4
CRS5
Carrier Sense - Ports 0 - 5. On detection of valid carrier (either transmit or receive
in half-duplex; receive only in full-duplex), these signals are asserted
asynchronously with respect to RX_CLK. CRS is deasserted on loss of carrier,
synchronous to RX_CLK.
O
O
O
201
85
64
46
28
10
COL0
COL1
COL2
COL3
COL4
COL5
Collision - Ports 0 - 5. Active High indication of simultaneous receive and transmit
activity. These signals are asserted asynchronously with respect to RX_CLK.
These signals are inactive during full-duplex operation.
200
72
54
36
18
206
188
RX_DV0
RX_DV1
RX_DV2
RX_DV3
RX_DV4
RX_DV5
Receive Data Valid - Ports 0 - 5. These signals are synchronous to the respective
RX_CLKn. Active High indication that received code group maps to valid data.
During 10M operation, RX_DVn is asserted with the first nibble of the Start-of-Frame
Delimiter (SFD) “5D” and remains asserted until the end of the packet.
Receive Error - Ports 0 - 5. These signals are synchronous to the respective
RX_CLK. Active High indicates that received code group is invalid, or that PLL is not
locked.
74
56
38
20
2
RX_ER0/RXD0_4
RX_ER1/RXD1_4
RX_ER2/RXD2_4
RX_ER3/RXD3_4
RX_ER4/RXD4_4
RX_ER5/RXD5_4
During 10M operation, active High indicates that the received data is invalid (SFD =
A2 rather than 5D.)
O
O
Receive Data - Ports 0 - 5. During symbol mode operation (16.11 = 1), these
signals are re-mapped to provide the fifth data bit (RXDn_4) for their respective
ports.
190
73
55
37
19
207
189
RX_CLK0
RX_CLK1
RX_CLK2
RX_CLK3
RX_CLK4
RX_CLK5
Receive Clock - Ports 0 - 5. This continuous recovered clock provides the
reference for RXD, RX_DV and RX_ER signals. 25 MHz for 100 Mbps and 2.5 MHz
for 10 Mbps.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain
2. The LXT9763 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,
where X is the register number (0-32) and Y is the bit number (0-15).
12
Datasheet
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