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LXT975AHC 参数 Datasheet PDF下载

LXT975AHC图片预览
型号: LXT975AHC
PDF下载: 下载PDF文件 查看货源
内容描述: 快速以太网10/100四收发器 [Fast Ethernet 10/100 Quad Transceivers]
分类和应用: 网络接口电信集成电路电信电路以太网局域网(LAN)标准以太网:16GBASE-T
文件页数/大小: 74 页 / 1026 K
品牌: INTEL [ INTEL ]
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LXT974/LXT975 Fast Ethernet 10/100 Quad Transceivers  
Table 44. Control Register  
Bit  
Name  
Description  
Type 1  
Default  
R/W  
SC  
1 = Reset port.  
0 = Enable normal operation.  
0.15  
Reset  
0
1 = Enable loopback mode.  
0 = Disable loopback mode.  
0.14  
0.13  
Loopback  
R/W  
R/W  
0
Speed  
Selection  
1 = 100 Mbps.  
0 = 10 Mbps.  
Note 2  
1 = Enable auto-negotiate process (overrides speed select and  
duplex mode bits).  
0 = Disable auto-negotiate process.  
Auto-Negotiation  
Enable  
0.12  
R/W  
Note 3  
1 = Enable power down.  
0 = Enable normal operation.  
0.11  
0.10  
Power Down  
Isolate  
R/W  
R/W  
Note 4  
Note 5  
1 = Electrically isolate port from MII.  
0 = Normal operation.  
R/W  
SC  
Restart Auto-  
Negotiation  
1 = Restart auto-negotiation process.  
0 = Normal operation.  
0.9  
Note 6  
1 = Enable full-duplex.  
0 = Enable half-duplex.  
0.8  
Duplex Mode  
Collision Test  
R/W  
R/W  
RO  
Note 7  
Note 8  
1 = Enable COL signal test.  
0 = Disable COL signal test.  
0.7  
Transceiver Test  
Mode  
0.6:4  
0.3  
Not supported.  
Not supported.  
0
0
Master-Slave  
Enable  
RO  
0.2  
Master-Slave Value Not supported.  
Reserved Write as 0; ignore on read.  
RO  
0
0.1:0  
R/W  
N/A  
1. R/W = Read/Write  
RO = Read Only  
SC = Self Clearing  
2. If auto-negotiation is enabled, this bit is ignored. If auto-negotiation is disabled, the default value of bit 0.13 is determined by  
CFG_0.  
3. If SD_TXn is tied High or to a 5V PECL input (FX Mode), the default value of bit 0.12 = 0. If SD_TXn is tied Low (TP Mode),  
the default value of bit 0.12 is determined by AUTOENA.  
4. The LXT974/975 internally holds all set values of the configuration registers upon exiting power down mode. A delay of 500  
ns minimum is required from the time power down is cleared until any register can be written.  
5. The default value of bit 0.10 is determined by pin TRSTEn.  
6. If auto-negotiation is enabled, the default value of bit 0.9 is determined by CFG_0.  
If auto-negotiation is disabled, the bit is ignored.  
7. If auto-negotiation is enabled, this bit is ignored. If auto-negotiation is disabled and the port is operating in TX mode, the  
default value of bit 0.8 is determined by pin FDE. If auto-negotiation is disabled and the port is operating in FX mode, the  
default value of bit 0.8 is determined by pin FDE_FX.  
8. This bit is ignored unless loopback is enabled (bit 0.14 = 1).  
64  
Datasheet  
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