Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975
5.0
Register Definitions
The LXT974/975 register set includes a total of 48 16-bit registers, 12 registers per port. Refer to
Table 43 for a complete register listing.
• Seven base registers (0 through 6) are defined in accordance with the “Reconciliation Sublayer
and Media Independent Interface” and “Physical Layer Link Signaling for 10/100 Mbps Auto-
Negotiation” sections of the IEEE 802.3 specification (Register 7, Next Page, is not
supported).
• Five additional registers (16 through 20) are defined in accordance with the IEEE 802.3
specification for adding unique chip functions.
Table 43. Register Set
Address
Register Name
Bit Assignments
0
1
Control Register
Status Register
Refer to Table 44 on page 64
Refer to Table 45 on page 65
Refer to Table 46 on page 66
Refer to Table 47 on page 66
Refer to Table 48 on page 67
Refer to Table 49 on page 67
Refer to Table 50 on page 68
Refer to Table 51 on page 68
Refer to Table 52 on page 69
Refer to Table 53 on page 70
Refer to Table 54 on page 70
Refer to Table 55 on page 71
2
PHY Identification Register 1
PHY Identification Register 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
Auto-Negotiation Expansion Register
LED Configuration Register
3
4
5
6
16
17
18
19
20
Interrupt Enable Register
Interrupt Status Register
Port Configuration Register
Port Status Register
Datasheet
63
INTEL [ INTEL ]
