LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
6.0
Register Definitions
The LXT971A register set includes multiple 16-bit registers.
presents a complete register
listing.
is a complete memory map of all registers and
provide
individual register definitions.
Base registers (0 through 8) are defined in accordance with the “Reconciliation Sublayer and
Media Independent Interface” and “Physical Layer Link Signaling for 10/100 Mbps Auto-
Negotiation” sections of the IEEE 802.3 standard.
Additional registers are defined in accordance with the IEEE 802.3 standard for adding unique chip
functions.
Table 41. Register Set
Address
Register Name
Bit Assignments
0
1
2
3
4
5
6
7
8
9
10
15
16
17
18
19
20
21-25
26
27-29
30
Control Register
Status Register #1
PHY Identification Register 1
PHY Identification Register 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Base Page Ability Register
Auto-Negotiation Expansion Register
Auto-Negotiation Next Page Transmit Register
Auto-Negotiation Link Partner Received Next Page Register
1000BASE-T/100BASE-T2 Control Register
1000BASE-T/100BASE-T2 Status Register
Extended Status Register
Port Configuration Register
Status Register #2
Interrupt Enable Register
Interrupt Status Register
LED Configuration Register
Reserved
Digital Config Register
Reserved
Transmit Control Register
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
Refer to
Not Implemented
Not Implemented
Not Implemented
Refer to
Refer to
Refer to
Refer to
Refer to
–
Refer to
–
Refer to
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
71
INTEL [ INTEL CORPORATION ]
